I2S, not I2C

@@einball Thanks for the correction.

​@@diggleboy You're welcome! I didn't want to be nosy but I also couldn't let the thought that 'someone is wrong on the internet' bug me during the night! :-^)

Good

Thank you. Someone else also mentioned this already. I would pin your message here in comment field..

did you just trust STM32 to finish handling each interrupt before moving to other ? or did you calculate how much time it would take to process data and compared to time it takes to fire each interrupt. I kind of got lost there. In case of FFT, where I believe you need to fill much bigger buffer (because of frequency resolution and etc) you would not process it before another RxReceived callback would be fired.

Do you have a link to your project's code?

@@giorgitsintsadze9919 What I do in that project is double buffering because I dont want to mess up with timings and disabling interrupts. So in case of FFT you can have 2 buffers of same size. One should gather data from i2s until is full. Once full you would switch to the other buffer and simultaneously calculate fft on first buffer.

@@edgeeffect nope sorry I cant share

I do have a question: did you ever compare the STM32F4 IIR filter response to the theoretical/calculated transferfunction? I find an offset of several hundert Hz and cant explain why (the true sampling freq. is lesss then 96kHz; but only 2% or so)...

Did you find the answer? Is it an error?

Hi! Did you ever figure that one out? I'm having that exact same issue on the F730. Thanks!

I guess I'll answer my own question: If the I2S unit has internal PLL it would suffice to disable the master clock output and use only the I2S2_CK line as input to the SCK of the unit. I think your setup use half word for the DMA, as this was working out nicely for me.

Yes there is an audio-codec on the board for audio output. However you don't have any audio input besides a microphone and you also have to configure the audio codec before with I2C. Using the PMOD I2S2 board here is quite more easier as you don't have to do software configurations first.

you got any answer

How did you distribute the clocking? What converters are u using? Did u check the I2S signals with the scope ?

@@YetAnotherElectronicsChannel hello! Just loaded up your project files and uploaded. Same boards etc as you are using in your video! Will have a scope tonight and see if it's something obvious. A fellow audio and electronics enthusiast so love your videos!

Damon McCartney what I was doing always wrong is that I exchanged sometimes the datelines from/to ADC / DAC ... and for sure the clocking signals like MCLK, SCLK und WS are only available once on STM side but need to be spreaded to both ADC and DAC. The 3.3V supply can be taken directly from the STM32 board

Did you try to compile my project? Was this working? Which device to you exactly use?

I²S is transmitting the data in signed integer format (means 2's complement) with the sign-bit being transmitted directly at the beginning. In 32-bit integer, the sign-bit is also most MSB bit. Of course you could shift the data low by 8, but you have to care, that still the sign-bit is on the correct position for also 32-bit integer data type (means that is not just a bit-shift but an arithmetic bit-shift). In the end it doesn't care if all the data values are scaled up by 255 or not. The risk in my implementation for sure is that you can get faster numeric overflows then if you are near to clipping level.

@@YetAnotherElectronicsChannel that makes perfect sense, can't wait to learn more from your videos !

O yes!..you found that to..:-).. I put that remark at the bug report on github Quick fix: comment out the Dma interrupt associated with the send

dan snazelle WM8731 will also work, but will need some modification as it needs to be configured before

@@YetAnotherElectronicsChannel yes i tried to build it :) but i am now reading it needs to enabled..however i am not sure where to do this. (seems it must be enabled via i2c?) anyway excellent videos.

Audio ADCs are typically always in stereo. There also some on the market which even have 4 or 8 audio channels. But always a multiple of 2. And yes, you can keep one input floating or connect to GND via a capacitor and then process only the samples of one channel inside the DSP

@@YetAnotherElectronicsChannel thank you very much for the quick answer

Marcel Dolnák have a look here: www.earlevel.com/main/2013/10/13/biquad-calculator-v2/ ... or if you are interested to calculate it yourself look here www.w3.org/2011/audio/audio-eq-cookbook.html

@@YetAnotherElectronicsChannel Well thank you :-)

No, since that board has no i2s, i also was researshing for that, and according on this site:stm32duinoforum.com/forum/viewtopic_f_29_t_4181.html, there's some way to make it work with i2s, but it would mean more work.

@@asunavk69 Oh but thats for the final part of the video. I just need fft and FIR lowpass filters. I tried a low pass filter and it worked perfectly. Thanks for everything and continue with the good work.

@@antoniomartos2343 idk what fft is but if a FIR low pass works for you then ok, did you do it with the l476rg?

@@asunavk69 fft means fast fourier transform for having signal in frecuency domain. FIR lowpass worked perfectly. Thanks a lot!!

Yes, 192 kHz is possible. Just checked it in the CubeMX Software.

Leonid Sobolev there is not sense behind 1 kHz high- and lowpass. It’s just a demo

The pinning of the STM32 you can see in the block diagram quite at the beginning of the video

@@YetAnotherElectronicsChannel oh, sorry I must have missed that detail..., thanks!

Check out roughly 3:10 for example

@@YetAnotherElectronicsChannel yep, there it is... I somehow overlooked it thinking this diagram was more conceptual 😅

@@YetAnotherElectronicsChannel Thank you your videos and code are very helpful. I'm trying to implement your phase vocoder to do pitch shifting in a DSP project i'm working on for school. I do have a question to solve a problem I've encountered: I see that the PmodI2S2 has separate pins for the ADC and DAC side, but both need the same clock signals: MCLK, LRCK (WS), and SCLK. Did you short these pins together on the pmod board somehow or did you configure pins on the STM32F4 to give you duplicates of the clock signals ?

Du hast natürlich recht - das ist bisschen verwirrend. Mit 96 MHz wurde das I2S Modul getaktet. Eigentlich keine valide Frequenz, wenn man die Audio-Clocks exakt treffen will. Korrekterweise hätte die Clock da z.B. 98.304 oder 49.152 MHz sein müssen. Damit würde man dann durch 2^x Teiler dann entsprechend die Frequenzen wie 24.576M, 96k, 48k, 6.144M treffen. Normalerweise reserviert man für das audio-clocking eine eigene PLL, die diese "krumme" Frequenz dann erzeugt. In dem Beispiel war die reale sampling-requenz dann eher 93.75 kHz statt 96k

I certainly wouldn't.

@@robertbristow-johnson6362 aren't interrupt handlers supposed to be as fast as possible? All the heavy processing then is done in the main loop or separate task.

@@assertivebird No not necessarily. In real-time DSP, we would put all of the sample-by-sample processing in the interrupt handler. If we are processing samples in blocks, then DMA would get the samples in and out, but the interrupt that occurs when the DMA is full would do all of the sample processing for the block.

Hanna Nabil u are right, 24 bit audio is actually transmitted in 32 bit frames. The 8 LSB are 0‘s

@@YetAnotherElectronicsChannel but when use DMA ( half word) and you use I2S_dma which take 16-bits data Does the I2S still preserve the 32-bit frame ?

Hanna Nabil DMA is working in 16 bit mode, but two 16-words behind each other are building a 32 bit word. You can cast the 16-bit pointer directly to a 32-bit pointer

@@YetAnotherElectronicsChannel you are right But Does the I2S will still send clock cycle for the least 8-bit even they are always zeros Um asking because I am using a codec with 24-bit DAC which let me choose between 24 , 32 bit I2S

Hanna Nabil yes there will be another 8 clock cycles even if it is 0‘s

Yes. You can enable DMA on both ADC and DAC, then have both triggered by hw timers. The samples will be interleaved so you need to split them. Use a DMA call back (as shown here) to process the ADC input. You will find that the filter order (number of taps), the sample rate and the max ADC clock speed are dependant on each other. For embedded systems the ADC clock speed has a max value much lower than "normal" systems. The sample rate will determine the sound quality of the output and should go no lower than 44.1KHz. Therefore, you will need to design your filter so that the order/taps achieve the required frequency response whilst not becoming too computationally expense to affect the sample rate. In other words, your ADC clock will be "maxed out" and it will be a trade off between sample rate and frequency response. As the cutoff frequency gets lower, the passband becomes narrower and it becomes increasingly difficult to create a cheap and effective filter.

@@thecrikster Are you talking ybout the IIR filter ? How does it effect ADC clock of the internal ADC but works fine with the external?

@@thecrikster I am doing a 2x vias Crossover (LP and BP) and the problem that I having is that I listen pulses but not "Music", any IN signal, the "Output" is a pulse.

Perhaps you could kindly make a detailed video on how you make it realized. I am still working on it for a week but no clue.

@@S-MKim I did fixed it... i was using male to female wires and ofcourse somewhere was no connection between pins. That was the reason.

@@S-MKim well i used 6x2 female header and i soldered pins to STM32F4 and worked.

@@kekecjan Congratulations. So the codes seem alright. I will buy a new Pmod I2S2 (mine seems dead) and try it again.

@@S-MKim yeah code works great. why dont you make your own PMOD I2S2 ? one board costs 50€ with shipping isn't that much for one PMOD? i made my own PMOD and work well... also i could make 5 of them for the same price. Up to you... all you need is already in documentation for PMOD.

it was intencional, for demonstration porpouses he did one channel for low pass and other for high pass, to have full low pass and high pass i think one would need dedicated class D's to being filtered digitaly.. Edit: that would be if one would amplifly on a speaker, to have low-high pass on stereo i think it would be needed to add the another I2S "comunicator", if you know what i mean.