1024 bytes eeprom on Uno, nano and pro mini. Mega I think has 4096 bytes eeprom.

General practice to have one large uf and one small for low freq and high freq. I just choose 10uf and 0.01uf for fun. no concern about current inrush green board ordered and tested. if found I routed 5v to the wrong pin on the arduino and that the switches were routed to analog pins that cannot be configured to digital inputs, the second revision i fixed the errors and ordered red boards. go to the pcbway website for a clear schematic

Inrush current is self limiting on such small capacitors. Remember that an ideal capacitor coupled to an ideal voltage source has an infinite inrush current. Little ceramic caps fed from very low impedance sources have stupendous inrush - you can get a 0805 capacitor size spike 10A or even more. A tantalum of this size has a couple tenths of an Ohm ESR usually, and that’s plenty enough, especially when fed via long wires. It does help to have a fast clamp across the power input on the entrance to the board, so that the inevitable ringing of the long supply wires won’t zap anything. Jim Williams IIRC has an app note about supply transients cause by low ESR capacitance that kill voltage regulators. Of course there are good reasons for low ESR capacitors, it just takes some proper design work and bench testing to quench all the spikes.

yes, I like the ones that program easily, unfortunately there are still new boards that still do require Boot 0

No. It was just too fast. I had to change to a 256 divisor

GPS disciplined is $100 and is easy. WWV is ok but requires practice and only when you can receive the station. rubidium is getting expensive and requires some DIY for power supply and heatsink. if you get an oven oscillator and can cal it (friend?) they are stable for decades. my old HP equipment are all still spot on (8591,8712,8921)

@@IMSAIGuy Hmm. How tricky would it be to make your board accept a 1PPS signal from an external GPS module as a timebase or special calibration mode?

@@ThinklikeTesla if you get an m8n gps it can program it over usb-serial to output a slightly dodgy, but accurate period, 10mhz wave

I'll be waiting for your build and video

​@@IMSAIGuy I did this design back in 2015 and I know I have the verilog code and the schematic for it. The project I was looking at in 2015 was almost exactly what you are doing here. Except the VCO was another product we build that has an external VCO control input which I was controlling with a16 bit DAC. My plan was to get the frequency counter calibrated then have the CPU step through 256 steps that covers the full range of the DAC and record the frequency in a eeprom to use as a look up table to get me close to the desired frequency then let the CPU fine tune it using interpolation. Unfortunately the project was a low priority and eventually died on the vine and has never been revisited. I have the first revision of the PCB here at home and I do have the verilog code functional for the most part but needs a lot more attention. Back then I wanted the FPGA to do all the auto ranging which was giving me lots of problems. If rip out the auto ranging features and let the CPU set the range / pre-scaler as needed that would make it much easier. If I use the prototype to work on the verilog code while I get the schematic trimmed down to just what is needed and then make a new layout. Famous last words "It shouldn't take me that long" but don't hold your breath! I have always wanted to make a frequency counter but I've never had a real reason to actually build it outside of work. I won't build something just to be building it, I have to have a need for it. I will give it a try and if I get it working I will send you one. But until then you should continue with your plan.

An FPGA for this is like going with a tank after a fly. There are high resolution single chip time-to-digital converters that make the whole thing mostly trivial and give you resolution and update rate that until recently was reserved for $2k+ instruments that has to implement interpolation on an ASIC. An FPGA will top out at clock rates that were no problem to direct counting (no prescaler) frequency counters decades ago. You can build a 1GHz direct counter using an ECL counter for the lowest digits, those are still being made. No prescaler needed.

pins 4 and 5 are i2c so they don't need defining

@@IMSAIGuy Perhaps I am using the wrong terminology - D5 is an input from the prescaler, yes? D5 is not defined in the code. SO, sre you using the I2C input for that? Or is it listed as some other pin in the code. I DO see A4 and A5 as the SDA and SCL lines to the display.

@@mstover2809 oh yes, A4 A5 are used for i2c, d5 is an input and should be defined as input. I guess it worked for me with out definition.

anywhere you want. anytime you need to go from top layer to bottom

I don't remember, eBay?

when the sea lions in the artic sleep on the ice, their fat takes on a squared appearance.