This training is part 1 of 2. Altera® Agilex™ 7 M-Series FPGAs introduce a hardened, but customizable, Network-on-Chip interconnect, or NoC, at the top and bottom I/O periphery of the device. Including the NoC in a design that uses an external memory interface (EMIF) or on-chip high bandwidth memory (HBM2E) reduces FPGA fabric congestion at the I/O and makes it possible to saturate memory bandwidth, even while running FPGA logic at a slower speed, making it much easier to close timing. This first part of the training discusses in more detail the advantages of using the NoC and explains the architecture of this unique device resource.