Hi All, thanks for your interest in another one of my videos! I was reminded on reddit to emphasise that the AW and W channel can both be written to at the same time, you don't need to write the address first and then the data. I do discuss it in more detail in part 2, but I realise the diagram here shows address before data, and that doesn't have to be the case.
@peterschmidt-nielsen357719 күн бұрын
Wow, this is super helpful, you really simplified it down, thanks!
@footballover01Ай бұрын
Thanks a lot! I love how data sounds like daughter, makes the video even more interesting :D
@donaldkelly30163 ай бұрын
You are wonderful!! This space is so underserviced, I am inspired and learning so much from contributors like you.
@raghavendraph85833 ай бұрын
Thank you so much. This really helps boil it down to an easily digestable format.
@FrustrationCrustacean Жыл бұрын
Thank you for making it a bit easier to get into hardware design
@ekbhatnagar Жыл бұрын
Thanks was searching for a comprehensive example on it for a long time.
@kortaffel Жыл бұрын
She's back! ~ 💖💖💖
@AustinTronics Жыл бұрын
Thank you for taking the time to make these!
@flytothesky1910 Жыл бұрын
Good to see you back :)
@slicer95 Жыл бұрын
Thanks a lot for the video Stacey
@FPGA_Frontier Жыл бұрын
Thanks Stacey, keep making video for us.
@etherbladenet8123 Жыл бұрын
Hi Stacey, great video, thank you. The only thing I think you should have mentioned is that the transactions diagram you shown at (0:09) is relating to AXI-full, not AXI-lite protocol.
@Jonathan-ru9zl10 ай бұрын
Thanks for the video! Keep up the good content💖
@timsmith9942Ай бұрын
Great video! Do you have a video about your way of documenting verilog code by chance?)
@rallymax25 ай бұрын
This was really great.
@jogeshsingh854 Жыл бұрын
Quite insightful 😀😀😀😀
@jsk40517 ай бұрын
Hi Stacey, thank you so much for your videos. These are very helpful :) One quick question, so ultimately these AXI4-Lite interface essentially consists of multiple AXI streaming interfaces correct? Is that the right way to think about this? Essentially AXI Streaming interface is a building block for AXI4-Lite?
@mutahargahaf7390 Жыл бұрын
😚😚😍😍🤍 Thanks for all videos , but please could you illustration the DMA and FFT (radixes 4) algorithm?
@angelg39866 ай бұрын
Stream interfaces are confusing: They say video is a stream, hence one should use stream DMA to transfer it, but i understand video as sequence of 2D frames. Each frame needs a buffer, it can't just leak as a sequence, so I think it should be memory-mapped...
@user-hf6kh4xc5r11 ай бұрын
I learned a lot from this video. thank you very much. ^_^
@FPGAsforBeginners10 ай бұрын
You're welcome!
@MrBryanstaton Жыл бұрын
I would appreciate if you did an spi_slave design using sclk as the clock edge. I know you would have to use block ram or a FIFO for handling a cross clock domain to the rest of the system. I rarely see this approach handled and would like to see how you would do it. Need is for the slow response time on cross domain clicking the spi cli and already running on slower fpga devices with 50MHz clock. The spi protocol can be very simplistic, very controlled usuage.
@arjunraj82814 ай бұрын
how to build a axi4lite sram controller from this code can u give a tutorial
@dilaygorken209310 ай бұрын
Hi! thanks for the video. Is there any way to us to reach that documents. Thanks
@FPGAsforBeginners10 ай бұрын
It's called the the AXI4 specification www.gstitt.ece.ufl.edu/courses/fall15/eel4720_5721/labs/refs/AXI4_specification.pdf