Course : Systemverilog Verification 2 : L5.2 : Interfaces and Modports in Systemverilog

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4 жыл бұрын

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Пікірлер: 17

@udayshankar1986 4 жыл бұрын

Very well explained...Clarified all my doubts....Tq u!! Keep doing the videos...............They might be so much helpful for someone like me who are not interested in reading boring books...

@SystemverilogAcademy 4 жыл бұрын

Thanks for the feedback!

@Narennmallya 2 жыл бұрын

Tysm for these videos sir. Helped me a lot 😀

@SystemverilogAcademy 2 жыл бұрын

Thank you for the feedback 🙂

@MK-mf2vu 4 жыл бұрын

hi thank you..nice video...

@SystemverilogAcademy 4 жыл бұрын

Thank you for the feedback!

@Nipulpatel143 Жыл бұрын

Amazing

@SystemverilogAcademy Жыл бұрын

Thank you for the feedback 🙂

@vonAdieux Жыл бұрын

in 3:42, where does that .request signal come from?

@SystemverilogAcademy Жыл бұрын

Sorry, it' s a mistake, it should have been some signal defined in the interface. Thank you for pointing out 🙂

@Shahidsoc 11 ай бұрын

i think u want to use ready@@SystemverilogAcademy

@kellypainter7625 3 жыл бұрын

Nice video but I don't understand why you need 3 clocking blocks when they all have the same offsets relative to the input clock. Maybe that is explained in another video? I gather that is for verification and I don't know a lot about that topic.

@SystemverilogAcademy 3 жыл бұрын

All 3 clocking blocks (CB) have same skew (default input#1step output#0;) and this will be the case of most of the CBs used in the TB. The same interface can be used in a master driver/slave driver and in a monitor as well.We need 3 clocking blocks to use it under different mode of operations. Note that the direction of signals in each CBs are different. Eg: awid is output in a master, input in slave and again input in a monitor. Finally thanks for the feedback :)

@mrinalgupta1564 2 жыл бұрын

How are you accessing request at 3:21 without simple_interface's object?

@SystemverilogAcademy 2 жыл бұрын

When you will use INTERFACE.MODPORT intf_inst in the interface instance declaration, that's similar to using INTERFACE intf_inst . Then you will access interface signals with this instance handle like intf_inst.signal