Yeah, tha name remind´s me that too XDD

So thats where the deja vu feeling came from

What goes round...

I knew I'd seen that somewhere before but I couldn't put my finger on it ! Thanks for the reminder ! :)

FX you...

There's only one video that comes to my mind at this point. kzfaq.info/get/bejne/oJiUq7tmqa-pfYU.html R.I.P. to both.

Intel is better

And I'm glad he didn't listen.

@@masternobody1896 intel is nr.2.

Nice Haiku

can u share us ur pic?

You make me laugh but at the same time I'm annoyed. This dude has a wealth of knowledge and insights, but he's HORRIBLE to listen to.

Absolutely!

Only dedicated 10 minutes. x2 speed is great.

20:36 actually for me..cause I wanted to see my name on the Credits... 🤣😝

Always guarantee when you watch a (Jim) #AdoredTV video ❎

@@johnnyxp64 Being a Coreteks patreon means having big pp

Yeah, A64FX has 1TB/s theoretical bandwidth and 840GB/s of actual bandwidth.

There will be a soft ceiling for textures butI think it won't be a limitation more a practical one. It'll be a similar argument to the difference between 8K and 4K. How much detail can you see before it's just FOMO.

loading nowadays is no longer limited by file size, it is limited by bad code. NVMe SSDs do many GiB/s, no game asset needs more than the blink of an eye to load. Sadly, developers have some of the fastest possible hardware available (especially in big-budget games and programs), so they have no need to optimize. Running the same code on an average PC then makes it unusable.

The biggest issue is poor telecoms infrastructure. Even in the UK it varies massively in speed, they're already trying to save cost and not put in full fibre.

@jayViant Talking of holograms: kzfaq.info/get/bejne/jJ2GY5iFmarMook.html

@@Mil-Keeway compression and bad structuring of data makes for terrible load times rven on high end NVMes. Games before the next get werent optimized for this, maybe except star citizen and arkham knight.

iExplorer has SHAKRA engine (as shown in TaskMgr) and if it was coded in Germany it would have a SAUSAGE Cache pipe... LOL

@@glasser2819 No, it would have a Bierfass (beer jar) pipeline ;) I am german, I should know. ^.^

The driver of AE86 was a tofu delivery man

SUSHI coming up next.

They make the Best capitors .

Proof?

@@absoluterainbow it was a tongue in cheek summery of this video and an pun at the end

Better how?

@@Toothily There are a couple of independent things. For one thing, there's no architectural upper limit to the number of vector lanes. Another thing is that the dynamic configuration of the vector registers allows better utilization of the register file (for example, if only a couple of vector registers are used, they can subsume the register storage of the other registers to get much, much wider vectors). Also, while that part of the specification is still a bit up in the air, there is an aim to provide for polymorphic instructions based on said dynamic configurations, which means that it's far easier for it to adopt new data types with very small architectural changes. They also aim to provide not only 1D vector operations, but even 2D or 3D matrix operations, which could provide functionality similar to eg. nVidia's tensor cores, except in a more modular fashion. There are more examples too, but I think this post is running long enough as it is. I recommend reading the specification.

@@chuuni6924 that sounds really cool spec wise, but do they have working silicon yet?

@@Toothily The spec isn't even finalized yet, so no, there's definitely no silicon yet. However, the Hwacha research project is being carried out in parallel and I know there's a very strong connection between it and RV-V, and I believe they have working silicon in some sense of the word. It's a research project rather than a product, however, so not in the ordinary sense of the word.

Really wanted to know, what you guys think/opinion about this computer compared to nvidia dgx a100?? Does it has equal performance or something? I really excited to know this. Thx :)

Don't you just love their Masonic logo? The honeycomb hexagon also known as the Cube, a reference to Saturn and the system we live in. Just so happens to also be in the beehive colours.

Kind of, yes! The PS3 used several DSP-like processors connected onto a ring bus - except that rings, as well as other pure bus like topologies, while being the simplest way to interconnect multiple regions on a chip have several inherent limits which restrains this kind of topology to a limited amount of locally adjacent cells which is why the kind of processor presented here not only has one ring, but a hierachy of rings topology: See this paper as an example for examining & describing different hierachical ring topoligy variants as on-chip interconnection networks, also called NoC = "network on chip" "Design and Evaluation of Hierarchical Rings with Deflection Routing": pages.cs.wisc.edu/~yxy/pubs/hring.pdf This has been a hot reseach topic in hp & scientific computer engineering for several years now. Another really old, formerly rejected but increasingly interesting & related research topic is "computing-in-memory", also "processing-in-memory" or "near memory processing" because the costs to transfer data between processing units & memory is, as mentioned in this video, increasingly becoming a limiting factor, see "Computing In-Memory, Revisited": ieeexplore.ieee.org/document/8416393 but also semiengineering.com/in-memory-vs-near-memory-computing/ & while the recent emergence of array processors like Googles tensor cores & other forms of neuromorphic processing units is clearly at least partly due to that, this problem isn't limited to applications using AI but applies to a much broader category of problems - the "bandwidth wall" is a thing.

@@FrankHarwald One of the biggest headaches of working with the cell BB was the relatively tiny amounts of accessable memory each SPU had (256kb IIRC). This meant you couldn't use a lot of general purpose algorithms and instead had to modify them to be streamable with high locality of reference - for some algorithms it just isn't possible to optimise in such a way.

@@SerBallister indeed, but modifying algorithms so that they run with a high amount of locality is something that you'll have to do for all data intensive algorithms anyway - no matter how much of it is done automatically, profiler-assisted or by hand - regardless of what the underlying architecture is because while all shared memory architectures will start hitting the bandwidth wall at some point, distributed memory architectures will be the only way to circumvent these limitations. & yes, this also means that algorithm that access a lot of memory from the same chunk in a purely serial way will either have to be modified to access data in parallel from multiple chunks (if possible) or remain bandwidth limited (if this is acceptable or if the algorithm is inherently serial).

@@FrankHarwald You should aim for that yeah. The SPU local memory presented an addressing barrier instead of a cache miss like on a multicores, all data has to be present in that block. Take a ps3 game for example. Some systems like physics and pathfinding can be hard to compress your game world in 256kb, the PPU had to work on that stuff and you then had the headache of pipelining the output of that into the SPU (e.g. animation) if you want to avoid stalls. Interesting chip but can be hard work, task scheduling and synchronisation is also not straight forward. I would prefer working with modern desktop multicores with shared memory.

of course it is

ticking them back, not forwards

They have been on the roads for years...

there is also all wheel steering at the wheels at the back too, look at this tatra video kzfaq.info/get/bejne/i5OlndOntMvdlJ8.html

lots of 3-axle garbage trucks in europe have frontmost and rearmost steering, pivoting around the middle axle basically.

@@onebreh pog realy ?

You call that innovation? Get back to me after you google 'Spork'

37 is not too late. God willing you will be learning well past 37 and even at 73.

I'm 101 years old and still learning!

@@Seskoi in base ten?

@@IARRCSim they opened schools on Mars - finally)

@@Seskoi I'm 1,009,843,000 seconds old and I push myself every nanosecond to learn more and more

I think people are going to get surprised when AMD announces Milan this year. Also, the Frontier 1.5 exaFLOPS supercomputer will use a CPU chiplet + 4 GPU chiplets + memory in the same AMD chip.

The question is, what is more EPYC?

I agree. With how many problems Intel has been having for the last 4-5 years stagnating them on 14nm, comparing anything besides other x86 CPUs to Intel feels disingenuous. If they compared this ARM chip to the actual current x86 performance leader (a 2U Epyc Rome server with 128 cores) it would be beaten by at least 2-3X. Maybe performance per watt would be better on the ARM chip, but the performance density would almost definitively be unbeaten.

​@@BrianCroweAcolyte This isn't the first time ARM was expected to be dominate. It happened int he 90's as well. In fact Microsoft made Windows NT compatible with ARM back then. There was big promise that RiSC cpus would take over the world. Well, that didnt happen, and i still dont think it will happen today or in the future.

@@aminorityofone ARM will probably continue to dominate the market where chips are designed for purpose (unless RISC-V takes that market), mostly because x86 isn't licensed to anyone new.

Kenta Aoki lol I noticed that too

Oof

The "die is cast" comes from the middle high German/English Gutenberg printing. The printed page came from a single die cast, which is why it was slow and expensive (though cheaper than the Monks drawing each page by hand). This allowed Bibles to be printed, helped people learn how to read, and bring education to the people.

@@ehp3189 That can’t have been right. Guternberg’s innovation was the invention of movable-type printing, as in having separate pieces for each letter that were assembled to make up a page. Printing an entire page from a single block was a technique that had been invented by the Chinese centuries earlier.

@@lawrencedoliveiro9104 Granted, but the expression goes more towards the assembled type set being cast together in a block and any changes to that during a printing run were not to be allowed. It was difficult enough that breaking apart the group and then reassembling it for one letter change was more expensive than it was worth. At least that is my understanding. I liked philologogy in college but they only offered one class ...

By embedding the hbm on the soc, the processor has a direct link to it and can therefore shift data at much faster rates. It eliminates a huge bottleneck by shortening the bridge between the two. With all of these extra cores, specific tasks can be assigned, and change more dynamically than ever. Think of it as a logic function: the various cores can change form based on whatever task they are doing, and without it bogging down the system like emulation, for example. All computing is algorithmic, this is just a more advanced form of it.

@@redrumtm3435 Sure, I get that, and that is a great feature/asset to have which is one of the reasons I've been super excited about this chip and following it since the mid 2018 but what I am saying is 32GB of HBM per die seems kind of small for data centre work loads so when you have a data set or even single file that is more than 32GB you will have to split it and send it to different dies which will surely be much slower than have the whole of the data sat in normal system memory where any free CPU can work on the data?

@@Speak_Out_and_Remove_All_Doubt The entire system works so efficiently that data can be transferred much faster. It can achieve much more, but with a lower buffer. The cores are designed to work as one, and vary when and where necessary to suit a particular task. Basically, the entire thing is the beginning of ARM's transition into a hybridised cloud system that works across all devices. This is how we will cheat Moore's law, and continue to push the envelope so to speak.

@@redrumtm3435 I know Coreteks is a firm believer that ARM is coming for x86, and I agree it will take over certain areas, but I think the PC space is so heavily entrenched in x86 I really can't see it happening but it's great that it is happening on the server side if its faster and using less energy. Coreteks also loves RISC V, i'm not sure which is has the better chance of challenging x86's dominance.

True story. Yes we will see 3D stacked CPUs with some kind of RAM on them. (My guess is 2023). We've seen GPUs already that have large HBM stacks "on-chip", and we will see them integrated to even more "on-die". Since Intel has invented its "Foveros" tech to avoid the Interposer layer and TSV's. It does seem like the RAM packages would be almost as large in die size as the CPU. (judging back to the HBM GPUs). Also, Remember the 128MB EDRAM L4 cache on the integrated GPU of Broadwell 5775C (2015)? Granted it was for the iGPU, but that was an early proof of concept of CPU+RAM, and took up a very large real estate of that chip. It wasnt market friendly, the proportions and cost were all wrong for mass-marketability, but it was interesting to say the least. Right now its probably easy enough to add a stack of 1 or 2 modern 16Gigabit DRAM die (=2 or 4 Giga BYTES), thats just my speculation. They've also been researching that micro-coolant-channel science as a real possibility lately. And you're right, the heat in the 3D stacks is the main issue. Everyones trying to stack the best way possible, its just a question of how. Then again, besides the real science of it, theres commercial viability concerns. The currently long-standing seperation between the CPU and RAM markets, means we get good prices on both. RAM as a commodity as we know it would be at risk if the 2 main CPU makers are integrating it onto a CPU. The move away from "memory modules" we all know and love would be too hard to do. Plus, think Apple laptops and planned obsolescence; they already solder the RAM on the motherboard, I'm sure they'd love it soldered right on the CPU. So we can buy $1000 CPU+RAM combo-chips and throw them away in 3 years when Chrome starts using 128GB of ram. I'd be more convinced if it was a small L4 cache idea, and leave system RAM alone.

he does NOT want to mentiion the downfalls , we can barely keep heat off our current cpus and gpus, so 3d stacked? nah the amount of power needed, and cost to switch a billions of severs ,no happening

Having things as simple as the video suggests would be a dream. Unfortunately, we'll keep having multiple levels of memory like we always have for over 50 years and different speeds, capacity, and prices per capacity for each. That means any software developers eager for better performance will need to continue optimizing for that complicated layout and be mindful of how it all works. Drastically more L3 cache would be great but there will always be demand for different capacities that strike a different balance on speed, price per unit of capacity, and capacity. RAM Drives introduced at kzfaq.info/get/bejne/bNagks6jqM7bj3U.html do a great job of explaining some of the tradeoffs between speed, price, and others between SSD-like memory vs RAM.

When it hits consumer it will probably have HBM3 memory with up to 64gb on die. Since you won't need ram and GPU, PCs will become micro form factor, imagine how many sockets for these monsters can u fit on standart ATX motherboard without chipset, pci-e slots, etc? :)) and u just need to watercool that bitch with AIO or custom loop. U can add for example 12tflops another chip when u run out of resources or add smaller performance one and they will stack together :) and then add most powerfull one when u get money :) and continue your life with 3 cpus and add one more in 5-6 years :)

@@johannajohnson310 I'm inclined to agree, there's only so much efficiency you can squeeze out of silicon no matter how it's designed.

Where can I read about that?

JustVictor 17 hehhe nice man

JustVictor 17 this technology and semiconductor field is the only place were we all can be together without any bullshit politics and drama of this cruel world.

Not all Arm processors are designed to go in phones. This one would draw way too much power to be usable. For example the i.MX chip in the Librem 5 and the Allwinner chip in the Pinephone. Both of them were not designed for phones but are being used anyway for their open nature.

@@deoxal7947 I know that dude ... but a man can dream ... The power of the sun in the palm of my hand.

@@deoxal7947 Dude, I want that chip in my wrist band.