I have been working with mosfets for years and I still learn things from you !

First video on the whole KZfaq that talks about this detailed aspects of MOSFETs. Keep it up Sam !!

I really like your videos ... It's very very resourceful for upcoming power electronic engineers.. Thanks a lot from India

will watch again as i learned so much i need to think again. thank you for detailed explanations on this topic.

Thanks for the great video. Your videos are always a great help for students and professionals alike. However, I would like to point out a mistake in this video. At 40:57, it is said that the nonlinear effect of the capacitor would reduce the switching losses. Here, you compare two cases, one with a "constant low capacitance" and the other with "high capacitance at low Vds and low capacitance at high Vds (nonlinear C)". The increase in C will always have a higher charge requirement for increasing its terminal voltage, resulting in increased losses. I think the "red line" representing constant C should start decreasing when Vgs hits platue region, consequently dropping Vds to zero by nearly 10nC. Whereas, in the case of nonlinear capacitor, the drop in Vds would extend beyond 10nC due to the increased capacitance as you have shown. Thus, the nonlinear effect of the capacitor (increased C in lower Vds) should cause an increase in switching losses.

This was very helpful lecture to under stand power mosfet.thank you so much!

Very interesting and very useful. Many thanks!

Thanks for your hard work. Another fantastic lecture. I am very grateful as I have learnt a lot from you!

very detailed and comprehensive. thanks a lot.

Fantastic. Thank you very much for sharing this, I found it helpful to a simulation problem I've been having just this week. Keep it up!

Awesome video! Mr. Yaakov you answered so many questions of mine! Thanks!

The lecture was very helpful. Thanks a lot.

Thanks for your hard work doing these videos.

thank you Professor. It was interesting & helpful.

Hello , thanks for detailed description of MOSFET Ciss and turn on explanation that is unique. However I have some critics here. Actually I watched the minutes 9:00 till 17:00 5-6 times and could figure it out the explanation. first of all, talking about the behaviour of an electrical circuit without writing the current/voltage equation is hard to understand. maybe writing the kirchhoff's law at the nods/meshes that you want to point out could help for better clarification. secondly the mouse pointer is showing point A when you are talking about point B for example . And finally talking "current/ voltage at this point or that point" is not clear which point. maybe it is better to define the currents and voltage as Ig or Vds etc... and mention them explicitly as gate current or drain source voltage. many thanks

Your lectures provide a very good learning experience.

Dear Professor, if you have some freetime, could you please make this lecture again? Since the cursor is shifted, one of the most important concepts of the Power Elecronics get quite hard to understand. Since your videos are quite intuitive, I almost only follow your videos. I hope my intention was clear :) In anycase, may the God bless you.

I guess the cursor in this tutorial being pointed to at, is offset by few scales depending on full screen or not :) !! But thank you very much for making this video. This was extremely informative and useful.

still cannot understand it will. Thank you this is very helpful

thank you for this

Hello. It was very beneficial, thanks. but I do not understand one thing. the flat area was formed because of that feedback effect and the transistor current is linked to Vgs. when drain current heat to zero, what difference makes the feedback effect and that linkage does not work here?

great job! very thankful to you!

Sir, the pointer is displaced. Will it be possible to rectify it sir? I am finding it difficult to understand a few points as I am a novice in this field.

I really like this simple explanation regarding the CGD capacitance. Comparing on and off State and calculating the delta Q for the input capacitors. What really confuses me is the term miller effect and miller plateau which are used in this context across the literature. From my understanding miller effect is something related to small signal calculation (gain). It has a huge impact on my bandwidth for example in my transfer function. Interestingly this simple calculation with the total charge reveals the same miller factor, that CGD is increases by low frequency small signal gain. Is it possible to explain the miller plateau by looking at the related time constants? CGD is larger then CGS (because of Miller, additionally the FET is in saturation region since VDS>VGS-VTH), so the time constant associated with CGD should be larger. That means that when i reach the plateau the slope of charging CGD will be higher then CGS, because CGS has been already charged RELATIVLY higher.

It could have been really good if while explaining about the equivalent model, you could have used the pen to show the direction of currents and voltages which you were referring. I mean you could have marked the path or the nodes while you were referring it as' this current' or ' this voltage' . Anyway it was a brilliant video. Thankyou.

Hi, great video with great explanation. did you happen to make an updated one with fixed cursor? 😊

Dear Professor, thank you a lot for the video. I have a further question in the subject. Is it possible to help me understanding how to use and "rescale" the data sheets curves in case of different operating points? Suppose I want to use the 650 V you used in some videos at 12 V only and with a gate voltage of 5V. How should I readapt the values of the data sheets for my application?

Dear professor, thank you for this lecture, which is really great, simple, but without unnecessary simplification. But I think there is one mistake. Slide 15 (time:~24min). You gave an equation for Ig1 as an average value. But after further simplification, it would be (Vt+Vgsf)/2Rg. I think the correct form of this equation should be: Ig(avg)=((Vg-Vt)+(Vg-Vp))/(2*Rg). Best regards!

Greetings professor. I am a fan of electronics. I've been watching your videos. I wanted to ask you about a possibility, because I had a circuit in my hands that was behaving a little strange. It basically had a load fed at 1.6v, whose current was 5A, but on the oscilloscope it had a weird oscillation. Could you consider that the oscillation was caused mainly by having a low voltage Vds in the off state in the Mosfet? I say this because if the Vds does not have great movements, then you have an increased Coss. Generally speaking, is that observation correct?

Then quasiresonant and resonant topology are free from this kind of losses? Is Better when converter work with ZVS or ZCS?

Good video, thank you. I still failed to understand why vgs is flat during the linear range --I couldn't follow the explanation of what is going on during this stage that makes vgs flat.

Awesome. Thanks!

Very thanks for your videos, it is interesting, just the point is to make playlists of organized videos in series.

It's confusing because of the mouse pionting

Hi Professor, Could you please help me by clearing my below two doubts? 1. When Vgs reaches Vth, the current Id starts to increase linearly with respect to Vgs. But during this period, Vds is high and also Vds>(Vgs-Vth), the MOSFET should operate in saturation region and hence the drain current should be increasing parabolically as per the equation Id=K(Vgs-Vth)^2..If MOSFET is operating in saturation region, then how the drain current is increasing linearly? 2. In case of R load, Vth= Plateau voltage?

What is obejective of this topic...I didn't get