@jumblebee6018 4 жыл бұрын
Quick access revision 1:22 design representation 2:41 Y (wye) diagram 5:08 more on Y diagram contd. 10:04 Behavioral representation 11:02 Behav. repr. example full_adder 12:28 Behav. repr. example (verilog boolean exprsn.) 14:42 Behav. repr. example (verilog truth table) 18:08 Structural representation 19:51 Struc. repr. example (4b ripple carry adder) 21:13 Struc. repr. example (conceptual repr.) 22:04 Struc. repr. example (verilog 4b RC adder) 27:04 Physical representation 27:49 Phy. repr. example (partial description in verilog) 29:10 Digital IC design (a quick look) END OF LECTURE
@arafay142000 4 жыл бұрын
Verilog HDL Complete Series | Lecture 3 - Part 1 | Data Types in Verilog HDL by FPGA made Easy. Subscribe to the channel "FPGA made Easy".
@user-yr1qd7nr8v 10 ай бұрын
very good video, it really help my learning
@Random.PCB. 4 ай бұрын
Very clear, thank you for your service 🫡
@meanpillscasper Жыл бұрын
Great lesson as always. Thank you.
@anirbanpradhan9870 7 жыл бұрын
sir can you tell me from where im supposed to get the slides for these lectures ? thank you in advance :)
@lazy.researcher 6 жыл бұрын
register for the course in nptel official website and there u will get the slide
@saisurya6858 5 жыл бұрын
@@lazy.researcher could you please share a link or google drive, where i can access those. Thanks in advance!
@arafay142000 4 жыл бұрын
Verilog HDL Complete Series | Lecture 3 - Part 1 | Data Types in Verilog HDL by FPGA made Easy. Subscribe to the channel "FPGA made Easy".
@VaishnaviN-hf3dq 3 ай бұрын
heyy did you get slides?pleaase share if you get
@TharunMalla 2 ай бұрын
where we can download the notes??
@mrpossible5696 5 жыл бұрын
20:01
@bidhanroy9295 10 ай бұрын
1 1 1 & 0 0 0 is not written
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