Perfect tutorial! You sir are the rare 0.0000000000000000001% of the population that can explain things properly!

one of the best explanation videos I've seen in a while.

Great video. I got it right away. Listening to Steve Wozniak talking about when DRAM started appearing and how they chose to go with it because it was cheaper, and how it had to be refreshed all the time, got me interested.

Thank you so much for the great series on DRAM!

This is much better and clearer than my prof's explaination, great work!

this channel have really really informative videos, please keep up with the good work, your explanations are perfect

love how you start at the lowest level of abstraction and work your way up. Makes this content super digestable :)

I really can't thank you enough for this clear and comprehensive explanation

Without any doubt this is the best video on the internet about DRAM. I salute you sir

you did what google or wikipedia couldn't do in 2021, respect for you sir.

00:40 : What is a memory cell and how is made? 3:50 : How are memory cells arranged together? 4:21 : How can you read the content of a cell? 8:25 : Why so much work for just reading a cell? Eheh 9:27 : Summary! I appreciated the video 🤙

An excellent lecture that very clearly explains the structure and principles of a dynamic memory. I wish you will continue to do so for the benefit of humanity and especially for students and engineers who want to know better and understand the principles perfectly.

Think about the sheer amount of knowledge involved in our digital world, all start from a transistor.

I cannot believe that this channel has that number of subscribers. It worths definitely thousands more than that. Well, thanks for this video i wish that u would be my prof...

Interesting video for people who wants to know more how things works.

Thank you so much for being alive in this world to help me understand how it work , best wish for you and your family.

This explanation is what I’m looking for, great man !

This series is beautifully done. I can only imagine the amount of work to create it. One point of correction is at 9:21 refresh interval is stated to be 64 ns, but should be 64 ms.

Nice and clear explanation for DRAM! Thanks a lot.

this is the best i have seen for dram working explanation !!! Thanks a lot for this detailing out in a understandable way !!!

Great job, sir. Thank you so much for this content!

This is number one explained video on this top. Sir, Lot of love from Bangladesh

3:05 "When the gate is closed..." that will happen only if voltage is applied to the Gate. But here terms are opposite as in a normal circuit switch. Also thank you for these wonderful tutorials.

very well explained, thank you! looking forward for your other videos.

Thank you!!! You make my Computer Science book must easier to understand. What I most appreciate about your video is the information is absolutely relevant to what I am reading in this dumb book.

Very good, well done !

Very understandable. Thank you.

this was great. way better job then my Prof. Thank you!

Very clear! Thanks a lot!

Best Tutorial ever. Thanks

Excellent explanation ❤️❤️❤️

The retention time should be 64ms, instead of 64ns. This is really a great video!!!

Thank you so much! this is great

Sir you are awesome

Awesome, I can easily understand the flow of the principle. Thank you for producing the tutotial of this topic. Any Engineer should know the foundation how memory DRAM works when it comes to read and write. Looking forword to finish the rest of the videos in the series.

it's perfect video with perfect explanation!!

Wow!, You've earned yourself a subscriber here. :)

Thank you Sir !

Thank you so much.

what is the sequential order to watch your videos? I want to learn about computer architecture from starting so have you uploaded other prerequisetes videos?

Perfect video :)

Really Amazing Video ... Kudos!

Excellent series sir.. the most required one. If you could add the differences between various ddrs it would be very helpful

This is excellent

This is so good, I feel like God guided me here.

thank you teacher !

An amazing tutorial you are great.can you please explain how to Initialization, Calibration, and Training the dram

Hello thank you sir.

Just wow!!

Great series, sir! Although i have one question... At 6:26 didn't you mean the charge would move from the WORDline onto the capacitor? Since the partially charged wordline is connected to them, not the bitline.

Do the word line and bit line have anything to do with the rows and columns of actual DDR SDRAM? In a x16 device, there are supposed to be 16 cells in a column -- how is this reflected in the topology of the cell array?

Thanks bro

Sir can you help me regarding how byte addressable vs word addressable dram would work?

thanks!

Using transistors and capacitors from an electronics kit, could I build 2 bit dRAM using this method? And if I felt up for the challenge, would it be possible to scale it up for like 100 bits? I love building electronics and am fascinated with how computers process 1s and 0s

Sir in the beginning you mentioned that the value of capacitance is 30fF ..Sir what technology did you refer to 65nm or 90 nm?

This is great tutorial. But it is not clear why precharging bitline is necessary. Also not clear is why the voltage on it changes by only a small amount (near 6:10) \delta{V}. Is it because the time duration for which the pass transistor is ON too short? thanks

Excellent explanation!!! I've never seen a more didactic video on this matter. I would like to ask you, which book do you recommend me to read, to learn more about the electronic behavior of computer components. I am a Mechanical Engineer with little understanding on these topics but I would like to learn more. Thanks!!!

Is each row or column a memory address in the 2D array?

3:33 but single fet transistor can only pass current in one direction drain to source ( forward bise ) . Then how same can do the reverse ??

Excellent video! Clearly explained and illustrated. If possible, I'd only suggest adding a bit of animation. Nothing fancy, just enough to draw the viewer's attention - sometimes it took me a while to actually see what you were talking about.

9:20 refresh operations occur approximately every 64ms as defined by JEDEC standard, not every 64 nanoseconds

Please can you explain to me how we determine the value of the bit for one particular memory cell, I did not inderstand very well How this Works. Thanks very much.

Why did you make Part 2 private ? It's a great video which helped mi a lot in understanding of RAM.

How the charge is getting transferred for and to the capacitor by applying voltage. i have understood one case that when the capacitor is fully charged and high voltage is applied to gate the charge gets transfer from drain(capacitor) to source (bit line).but how come the reverse is happening means how zero vol capacitor getting partially charged after getting read(means charge is getting transferred from source to drain).could you please explain it sir.

Are bitlines disconnected from ground by the sense amplifier?

Your voice rings a bell. 😊. That physics channel. Right?

How long a second is😮😮 really great tech

9:22 the refresh duration should be 64ms instead of 64ns. Am I right?

if BL=1.5V and Vcap=3V, then in reading operation the Vcap will drop to 1.5V, right? How do you do stop Vcap to drop that much?

Thanks for the amazing content! There's one thing I don't get. Why should the cells containing 0 should be recharged? If, after all, they are not charged hence representing 0

what type of transistor in used in Dram cells?

❤️

what happens in the capacitor whe the gate is closed, does it remains charged or uncharged??

Same videos for SRAM ? :)

I saw in another video that DRAM cell refresh interval is 64ms, not 64ns

If I understood you correct, you described the bit line both as reading and writing, i.e. discharging and charging the capacitor. Furthermore this just playing with one of the two bits, the bit 1. And the bit 0 is just there for looks. How that cell is kept out of the way of being detected by means comparing its voltage .... is not discussed at all. Do you mean to say that in order to charge ( write) the capacitor the gate voltage is lowered and once it is charged the voltage of the gate is kept high? And since the capacitor is never fully discharged, for it to be charged the bit line of course has to have higher voltage and for it to discharge the bit line voltage has to be lower. And you haven't mentioned the value of the gate voltage. And for the capacitor to charge or discharge you have to send current to the gate? If so then so many cells are connected in a row all them cell's gates are getting current and the 0 discharged cells will get charged for no reason, i.e. being written to while the other 1 bit cells getting read or discharged. I see some charging ( writing) that has take place in the second row ( the first the the third cell) on the 0 bit cells, while the other two 1 bit cells are showing slight discharge. So I assume that the 0 bit cells in order to be read, some charges are sent there and then immediately has to be discharged somehow.... not sure how that is done. Espcecially if it is ROM memory. It shouldn't be changed.

🤩Wow

What happened to them cells with no charged capacitors. The 0 bit cells? How do you read those and why have a capacitor there anyway? Unless it is there just in case you want to change its value, changeable. What about the ROM. Are there capacitors there in the 0 value cells and for what unless it is there to change its value too? Maybe it is covered the next video. So far very informative.

I think the location of source and drain terminals should be interchanged

Please prepare a discussion on enterprising

@3:47 "you can see that 'reading' the content of a memory cell is a destructive process". Why? I understand it would be if you were to replace a 0 with a 1 but not why it would be simply reading the memory cell.

Speaking of DRAM, a dram is a unit of weight 1/16th of an ounce or 1/256th of a pound. Please help spread awareness of the dram.

In case you are like me. Making this in "Circuit Wisard" what Transistor do you need? my reset whit backfire power. So problematic when power open it self, or do other things like open the valve the other way around and other funny problems. No both ways Master Transistor that say: "you shall not pass" when not open. "i can't find the Gandalf Transistor" :-D And my free version P Ch MOSFET work like N or not working.

"So, Nice VideoFilm About DynamicRandomAccessMemory." Dr.HunterAgoldbi

how about static ram

approximately every 64ms NOT nanoseconds.

yay i am viewer 7000

if the all transistor were to be with one capacitor in 100% voltage and other in 0% voltage, then right now is not neccesary to higthering or lessering that capacitors voltage, but on its output sind capacitor get one switch to be output in cero or higt signal... so the reading or writing are synchronicse with output switch and clock to new data or registres, for that the transistor conmuting to Zero or high level if only signal input is in the shiper instant and about gate diode to be negative or positive voltage to ok output being one 1 or 0 digital binary... so our only get free the rampe clock active with the signal binary, in concluscion we only spend the more lessering 1% energía that other system ram, rom or cpu... esto sumado a la refrigeración líquida obtendremos celulares frías o pantallas frías por láser optico... rendimiento al máximo y velocidades muchos mayores de Ram o rom... 👽👽👽

core memory but its voltage instead of current

😢

mate youve given years of wondering a meaning.