Fraunhofer IPMS offers an IP Core processor based on the RISC-V architecture. This open instruction set architecture (ISA) enables the development of highly application-optimized RISC-V processors. The IP Core EMSA5 is available as a general purpose variant and as a safety variant with an ASIL-D ready certification according to ISO 26262: 2018 for functional safety and is therefore suitable for use in safety-critical systems in vehicles. The EMSA5 is supported by several IDEs and thus enables efficient and professional software development for complete systems, also in the context of functional safety according to IEC 61508 and ISO 26262.
More information: s.fhg.de/KI-maintenance