i didn't understand this at all during class. this helped me out so much. thank you!! - love from sydeny, australia :)

I can't thank you enough brother. I am like preparing for my upcoming ITPEC exam and this one D Flop timing diagram question is freaking out my last two brain cells.

This is so well explained, thank you so much!

Been struggling in this class, you've helped a lot.Please continue to do these videos. Love from Texas.

You just saved me! Thank you for this video! I've been strungling with this one in upcoming exams, 3rd try, since I haven't been able to understand this. You showed how to do it and didn't just explain it with words. That way it is so much more clear to understand rather than just in slides and explanations in text. Thank you!

Bro, thank you so much. Awesome and simple video. Thanks a lot.

You have done a great job in clearing the concept of timing diagram. But I had one question, can you please solve it? A circuit is made with two D-type flip flops. Assume that Q0 and Q1 are both low initially. Sketch a timing diagram showing the waveforms of CLK, Q0 and Q1 for the next six clock pulses.

so good. You did a great job. direct to the point

insaley good video. very clear and straightforward. cheers!

very good explanation. thank you!

Great examples, awesome explanation!

Awesome explanation. Thank you!

you are tooo good

Omg thank you so much, my man you are doing some good work, keep it up!

awesome video. helped a university student out in canada

Perfect

bro sukran to u, u did better than my sonfofabıtchteacher

Thank you so much mate this was very helpful

Thanks bro, you're amazing!

Thank you!

This is so helpful, thanks

Useful. Thanks!

It was extremely helpful. Thank you

Thanks for the information. Helped a lot

this video is absolutely grreatttttto

bro you are amazing

best explanation thank you

I think you just helped me pass a final omg

Excellent explanation

Great Explanation

thats so helpful thank u

you saved my day

Thanks for this👍🏽

Sir thank you for doing this ! I have one question for the D Flip- Flop, concerning how we draw the D diagram. Is there a pattern to it, or we can decide ourselves how will D look ? And as I understand, each time we try to draw the vawes for the D flip flop, we can have different output IF we draw a different D diagram ? Thank you !

well explained...

you are better than my prof

Thanks for the vedio

What a gold video

Very good

Completed your 1000 likes Thanks me later😊

❤❤❤❤

Nice

Clearly explained

Based

Brilliant video! But does the diagram D the same all the time? Or we can draw the diagram D which we want and diffent every time?

Can we call the clock input to the latch as an asynchronous input??

I had a question about the timing diagram. I was told it was called Delay because of the timing delay so would that mean that on the timing diagram, a delay would be needed or not (cos I saw you didn't add that)

how to post screenshot, you talked about. btw thank you!

hmm,it seems good i got an assignment can you explain me that with timing diagrams

Sir please explain the positive ff to positive ff and positive ff to negative ff combinations

What will be the output from a high level sensitive D latch if D=1 and the clock is high ?

if input signal is not given,how to take input signal such that all conditions showing in timing diagram?

What is set and RST?

sexy bro .... fire

What is the main difference between D-latch and D-flip flop

Why you are use clock signal for D-latch?

and my question is ECE GATE 2012 paper,30th question

Bro what are Flip-flops negatively triggered and what are all positively triggered

I think there is no clock in latches clock is in flip flop

i cANNOT UNDERSTAND

I DID NOT UNDERSTAND 3:00