Join us to discuss this and the other videos on discord: discord.gg/jmf6M3z7XS Support the channel on Patreon: www.patreon.com/JamesSharman

WoW! This reminded me of my BS graduation project in 1998 when I designed a RISC pipelined processor and wrote an assembler for it along with an emulator. The tool was used as an educational aid for freshman students in computer engineering department.

Seeing such a striking difference between machines that need multiple cycles per instruction and one which can (occasionally) reach the limits of scalar thruput is quite incredible

Fantastic result, James ...and to do it with discrete logic, incredible! Happy 100th. I wonder how many hours that is?

I absolutely love what you've done and always look forward to new episodes. You have all the reason to be proud!

That's amazing. It was really fun to see the step through of the pipeline!

Thanks for the shout-out, James! I hope to start looking at your system soon.

Curious to find out how fast you can clock this. Lovely processor, I feel blessed I was able to watch you bring it to life. Bringing this over to VHDL could immortalize your design. OpenCores comes to mind.

Nice work! Getting 3MIPS out of a 4MHz clock is certainly not bad. Not bad at all! A hundred videos in and I am still intrigued!

Congrats on the 100th video! Loving the series. :)

Excellent work! Amazing up to 100! Really appreciate the deep dive into the bench-marking. Thanks.

This is such a cool series. I've not gotten to watch everything yet, but working my way through it. I've managed to get a good handle on basic CPU design, but pipelining was always just out of my grasp. Thanks for showing us the work!

This is a fantastic labour of love, James. I've been binge-watching the whole series including the VGA implementation over the last 2 weeks and finally gotten to the end. I've really enjoyed your journey with logic, layout, soldering, video editing and presentation. All done with a good dose of British self-deprecation! Your presentation skills are excellent in my opinion. Certainly they are superior to many university lecturers I had on the same topic back in the mid 90's! :) Your coding skills are head and shoulders (and then some!) Above my own but I share your curiosity for just how far ideas can be taken using the hardware of the day and newer ideas. I wrote down a list of about 10 ideas (for improved signal integrity, latency reduction, stability) and another 10 architectural ideas that were used in the 8-bit days (almost! ;) ) that could give your project another huge performance boost. Probably way too much text to drop into a comments section so perhaps let me know if you're interested.

You've put an amazing amount of work into this! Really impressive.

Thanks for your hard work! I really wanna see where the project goes (and future projects)! I know this won't go too far with the costs, but I'm sure you'll put it to good use!

Awesome results. Congratulations on both the speed of your CPU and reaching 100 amazing episodes for it. Thanks James, take care.

Amazing work. I have really enjoyed watching your videos.

Awesome job and fantastic series. I am especially amazed at the way you approach things and how you managed to bring you original design to reality. Like I heard someday in a movie which name I cannot even remember : „I like how your brain work“ ;) very inspirational! Thanks a lot for sharing it all. And please go on !!

Great work James, I will be following your work for sure!!

I am surprised I only seem to have discovered this channel today. Brilliant stuff. Looking forward to watching the preceding 99!

This is an astonishing achievement - well done! Really brings home why the pipeline is so useful.

Love the design, and the results! Congrats on building this very cool system. Subscribed and off to check out your other videos!

Congrats on the 100, and congrats for the inofficial crown in performance. Reminds me of the crazy headaches we had in the 80s to create some nice pixel graphics ...

Fantastic results - genuinely impressive work, and a great project.

Congratulations, those are really impressive results! You should indeed be proud. I'm still surprised that, after so many videos, the subscribers and views on this channel aren't at least an order of magnitude larger. Thanks for all the great content!

Very interesting, the artificial NOP and instruction fetch stalling very well demonstrates why an instruction cache is needed, especially for a superscalar CPU.

Wow, what a great result - well done mate! Time to start work on your 16bit CPU !!!!

Such a cool achievement. Well done and thanks for those fantastic videos

You're a joy to listen to, and this creation is a joy to behold. Cheers.

Good to see you back, and of course congrats on the 3 mips :)

A very impressive result and a great 100th video. Shows how pipelining is far more efficient at running code than micro-coded CPUs. I watched the 8-bit Battle Royale when it first came out and wrote a Mandelbrot for the CSCvon8 and got it to do 32x22 with max 16 iterations in about 2 seconds running at 6.3Mhz. Took me quite a while to get the 16x16 bit multiply to work but when I got it right it was magical to see the Mandelbrot set draw on the screen the first time.

Wow, this is really impressive ! I really love your attention to detail when you explain things and I really love coming back for the know-how you share. I benched my own version of the X16, and it came in exactly as predicted, running at a simulation 4Mhz with no other real hardware than a 65C02 CPU. But your 1.3 is just so out of this world comparably.

Congratulations, that's an amazing result. It does make me wonder what sort of speeds would be possible if the CPU could be fabbed on a comparable process. Oh, and happy 100th video in the series.

A great video, and a great way to mark the 100th episode. Mandelbrot plots are always cool. It's fascinating how the incorporation of pipelining improves the IPC performance compared to machines without it. Of course, un-rolling loops and similar tweaks can also help further if the algorithm allows and one has the patience. ;)

This is amazing! Cool project!! 👏👏👏

Fantastic work, James! Love it! Keen to see it progress!

Excellent video! Subbed.

Excellent work! I'll admit that I didn't expect this big a margin.

If I understand this well, (similar to) this could have been built back when the selected CPUs were the stars and this compares really favourously. Huge work in outperforming the 70s chips with discrete logic - likely an achievment for life! Keep on good work!

I love watching the LED's and how it shows what's going on. Really awesome setup. I kind of want one on my wall just blinking away.

Impressive work, well done!

Wow! thats so cool 😎 james.. I have always had day dreams wondering how far 8 bit could be have been pushed without 80s budget constraints so anything like this I find fascinating.

Incredible. Awesome work.

Great to see the results here. I was a Z80 man myself in the 1980's, with the likes of TS1000 (AKA Z81) and Spectrum 48 within my repertoire of experience. I went straight to an IBM clone after that during my CS studies, but the Spectrum gave me lots of pleasure. One of my favourite games was Basil the Great Mouse Detective, chess, and a few others. Wrote my own 3-line editor. I tried making a full-screen editor, but it was painful watching the screen repainting after each keystroke. 3 lines were perfect. Boy what a trip down memory lane and I have you to thank for that James. Will you be re-inventing a sort of hard-drive for the computer? I would watch such a series. At this point I almost think you can build anything.

100 episodes! Ace! You went from something to watch when I was bored in hospital to one of my favourite KZfaq channels in about 3 episodes. Keep up The Great Work! :) In "the great debate" at college, we always said the BBC beats the spectrum and the 64! When they break down into CPU type, it makes sense.... Lots of pipelining wins, and smidge of pipelining comes second, no pipelining loses. Shame, I was always quite a fan of the Z80 back in the olden days. When I'm in 8-bit land, I'm doing assembler on AVR microcontrollers... it'd be very interesting to see where that would come in the leader-board.... need some way to get VGA out of it without eating every single one of it's clock-cycles though.

What an amazing project! When I was young, I thought I wanted to be a microprocessor designer, but this stuff is way over my head.

Congratulations! It's a huge milestone.

I have really been loving this series.

The 6502 is my favorite processor 😍 love what you got here!

That's ... fascinating and awesome. Congratulations.

I was wondering what you'd do for the 100th "episode". Benchmark is a great idea!

Congrats on the 100th video mate!

This is stupendously good! Blows the hat right off the Commander, and running at 4MHz no less... Now I really want to go back and watch how the pipelines work. Also I do wonder how much FPGA space an optimized version of your architecture would require. And I kind of want to try writing code for it!

It's amazing that you can out perform a CPU chip with all the transistors packed together with your CPU with the components spread out over 10s of cm. Fantastic project. And your presentation skills a perfect for a project like this.

Had to watch again. And I know I will watch it again.

Just found this channel, and I've been binge watching the series. It's amazing. I hope when it's completely finished, this computer is offered as a kit as an education resource, the same way the Cerberus 2080 is. It could be an amazing resource. I'd love to assemble one and learn from it. I would also love to know if this design can be implemented using CPLDs or an FPGA. Cheers!

Awesome! Congratulations!

What a fantastic job! Thanks for sharing.

Happy 100th! 🥳🥳

Not sure how I've missed this project but it's fantastic that you can get the performance and display with 8 bits on discrete logic.

I discovered your channel lately but i have to watch the full series

Congratulations, you have earned your success ;-)

Oh yeah, that's awesome! I knew this thing was a beast, and seeing it absolutely smoke the competition brought a massive smile to my face!

Congrats on the 100th, love your work.There is a modern Z80 called the eZ80. It can run at 50Mhz and has a 3 stage pipeline. I wonder how it would do running the Z80 version of the benchmark. One day I will have to give it a try,

Hi james. Amazing 100th. Have you looked back at your first videos ? It's amazing what you have achieved. Both in terms or CPU and in terms of video quality and editing. Looking foward to the 1000th 😉

What a fantastic project and an awesome achievement. It's hard to believe that this was how early processors were designed and tested, with lots discrete chips on boards, all spread on a desk. It's even more amazing that today, all of that can be fitted in to a tiny little package smaller than a fingernail and can be purchased for pennies. My first computer was a Sinclair ZX81, which I thought was a miracle of miniaturisation. 😁

Excellent result! Some of my first computing was on a CDC6600 which had pipelining and some asynchronous operations - did 3 MIPS but with 60 bit words and core memory. One of the most important architecture inventions in the 1960s was of memory cacheing - why not give that a try? If your code is doing a lot of localised fetch/store ops it can help a lot to resolve the cpu/memory speed mismatch.

fantastic, congratulations !

Outstanding project. I originally learned to program on an Apple II so I appreciate just how incredible the results you've attained are here. If you have hardware support for two stacks and implement a forth for it you'd have an extremely productive computer in terms of time from concept to effective and efficient implementation.

The pride you exhibit regarding this computer is VERY justified! Your work will not only help many people in the future understand the low level details of how computer systems function, but will also show the magic of following a dream and making it reality. If I had enough thumbs you would get a ten thumbs up from me for this series. (I think it is probably the best digital design series out there.) I'm personally not surprised at your results on the Mandelbrot set. The old 8-bit CPU's were designed either to fit what technology of the day could cram into a single chip, or were designed to a price point. It would be interesting to see how your processor stacks up to even some 32-bit processors of the day, like the Motorola 68000 or even the first ARM processor. I think you might beat the 68000, and come in for a close second to the ARM chip.

That's really fantastic. It may be an faq but since you have most of the logic transferred from breadboard to pc's, do the Gerber/Eagle/kicad files exist somewhere? Or even the schematics?

Fascinating work. I'm surprised your processor - spread across your desktop - is faster than the classic 8-bit. I also appreciate the 'normalized' performances. I was surprised the Z-80 performed so poorly. Congrats on a great result. I'm subscribed - continued success!

Thank you, I just found a channel to watch during my insomnia!

wow, it looks gorgeous. It is so well layed out. I know exactly how it would look had I made something similiar

Great work!

solid mate. And no bullshit. Extra marks.

That's an awesome result 😊👍

I've been following this project for some time now (not from the first, but close enough). I know you've tightly focused on your original objectives -- 8-bit, pipeline, SSI TTL-compatible chips for most everything in your CPU proper, but using LSI EEPROM and static RAM because life is too short to try memory solutions from TTL's heyday. That said, you have augmented your design with very useful hardware I/O. Have you considered adding a simple EEPROM (or, better yet, shadowed ROM in RAM as you do for your too-slow EEPROM) precomputed lookup tables for 8x8 multiply and maybe scaled fixed-point reciprocals, square roots, trig functions, etc? Allocating some registers in I/O space (or memory-mapped I/O) for a sort of table lookup maths coprocessor could be very interesting for increasing performance without adding complexity to the CPU. You are already using various sorts of LSI ROM & RAM techniques, so this would still be in the original spirit of your objectives. You needn't add more than one such lookup table at a time, as long as you have some unassigned I/O ports left. Multiply would surely be worth it, and reciprocal lookup does away with much of the heartburn and many, many cycles of long division. Most division problems in your use case would be reduced to finding the reciprocal of the divisor, multiplying that by the dividend instead of doing regular division, with either pre- and/or post-scaling to get the significant digits you require.

Dude, this machine is incredible! And at 100 parts no less?! How did I miss this??? Regardless, I hope you keep up with making this the One Computer To Rule Them All! ...my question is: what will this incredible miracle be named once it is all completed?

Excellent work! This is nothing short of amazing! Say, does that Mandlebrot use integer or floating point arithmetic?

Awesome results!

Great video! What do you think was the greatest limitation on the original 8 bit processors, to stop them reaching the same relative performance levels: cost of silicon, manufacturing limitations, lack of prior knowledge, or complexity?

It's got to be the fastest 74 logic 8 bit surely ?. And to say it has been designed, built and programmed together with VGA, sound, and UART, again all by 74 series logic by just one man is extremely incredible. I would suggest naming it _"The Sharman 74"_ . The series has been brilliant from start to finish and I will watch them all again. Fantastic. 👏👏👏👏

Awesome! Great result 👍🏻

That thing is amazing. I am amazed.

Is it geekish to say that this is really cool stuff? 😉 Greetings from germany, Marcus

Awesome :) Would be great if the next step would be to create the cpu inside a chip ;) fpga, maybe ?

WOAH!!?! Brings me back to my Intel 8051 microcontroller frustrations! The Assembler / development environment / ‘emulator’ ran on a DOS terminal. And so it was always a riddle to me, whether the ASM program was really yielding clock cycles and values that were true to not just it’s own software programming, but if whether that software was seriously delegating every 8051 resource appropriately, in the same order, initializing it’s registers, clearing its carry(s), setting up for parity, etc etc. And doing this initialization process just as some specific microcontroller’s data sheets had described. I find it rather amusing, the remaining two camps still to this day, who either prefer the clock’s ticks to be left up to X-tal wiggles, or by way of the RTC, driving those cycles over Transistor-Transistor-Logic. It seems to me That the TTL solutions are better geared for say a clock radio or a microwave oven, and the crystals are something that I would have to hand and so I’d grab it. THANKS A BUNCH FOR SHARING THIS, VERY GREAT LECTURE!!

So the true race is IPC, not MIP. This is a pretty impressive result for a single pipeline single alu cpu, a more dynamic register file with an in-pipeline register renamer would boost it a bit, so would a dual headed ALU. I’m also starting to understand why so many CPUs did a multi bus design instead of a main bus.

Nice result. Do you have any plans to port over a higher level programming language? Coding everything in assembly has to be tediously arduous.

Matt should have add your benchmark score. Don't get me wrong i love his channel too. But did he give a reason why? Don't understand he does have the X16 in his benchmark that even use an FPGA. I love it that your cpu/homecomputer is build out all on discrete IC's. If your project is finished i will probably order the kit. Nice job James.

amazing build.

I wonder, how would your computer compare to a commercial discrete logic computer like the PDP-11? Or even a modern AVR or PIC...

Great stuff.

Cool build.

I just landed here after starting from video #1 and then looking through easyeda: It would be interesting to see how much ground bounce you have on the cards; Most of them have very few ground returns compared to the large number of capacitive signals they are driving, and the edge rates are not that low. Signal-integrity and EMI worries aside, the architecture is just neat, and I can see why you left out an interrupt (more PC/RA registers, or a hack with the fetch-stage injecting a sequence?).

Congratulations!

Might make an interesting “load/efficiency” display to have a couple counters, maybe a subtractor and some leds to display a running IPC of sorts? 😎

Yeah, I'm just wildly impressed. I was also glad to see that the 6502 , as I always expected, turned out to be the boss of the home micros :-).

Have you considered adding instruction reordering capabilities to your assembler to minimize the number of NOPs?