Big thank you for making these publicly available. I do study in an unrelated field but I have a background in EE. I still find EE and CS very interesting and I want to understand more than just the fundamentals, so I hope I will enjoy the course :)

Thank you very much for making this available to everyone. I am truly enjoying the lectures and assignments. I intend to slowly go through as many the lectures as possible and document any findings, research results and answers to exercises which I will be glad to share with you if you are willing. Thank you for the excellent work that you do to advance technology for the future.

Information costs next to nothing to duplicate. To *not* have quick free access to valuable information which was already recorded should be a moral outrage. University shareholders and boardmembers are all parasite scum.

Soon that job will be outsourced or you’ll be fired when the project is over. Automation will take away these jobs first. You are not passionate about it why do it? become a lawyer or doctor for money not this.

@@cardcode8345 1) I am passionate about these and that's why I'm learning these outside of school. 2) As someone who is in academia, I can tell you that the only way to stay on top of automation is to know enough so that you can create these automations yourselves. Automating lower level tasks is how CS moves forward. But it takes another CS student to actually create these automations.

@@cardcode8345 lawyers don't get paid well anymore

@@cardcode8345 in addition you can start a business thsts about telco or a tech company yiu don't need a job

@@princealmighty5391 Legal jobs will be done by computers soon.

hes my teacher, check out "onur mutlu lectures" here on yt for a whole 2nd semester course for computer achritecture.. there might even be a master course on there..

Got it bro

thank you

What's the name of Patterson &Hennessey 's book

harware/software interface

Thank you 👍

why is he not uploading , it's 3 years since last upload

@@bzalpha236 His new lectures are here, kzfaq.info/get/bejne/pKdkh5ukqLa7pJs.html

@@deepanshumody4739 Thank you!

lol similar story here - Msc Ph - now what? time to learn python and computer stuff I guess...

lol

You think us nerds are attractive? Damn!

Hot as hell yo!

Indi bildim türk olduğu

Yes

Thank you for your info. I was trying to pick one series to follow:D

Is this course good to learn in 2024 or the latest ones? I find this one interesting please let me know

@@gayatri5397 it is. Are you a CS/CE student?

What are u saying man

Im 15

@@asafcohen3562 You lucky bastard

indeeeeeeed !

loved your comment yo!

​@@456bhavana These lectures are legendary

We pay in data about you collected by KZfaq that they then sell to whoever will pay. But I get you.

Stonks

aieeeen mote aieeeeen!

Absolutley 100% why I am here lol

Unfortunately there aren't many jobs in the field of hardware engineering even in countries like USA China and Japan that actually produce the world's hardware. Web development, networking and AI have way more jobs so less ppl take this course in college

Abhishek Kumar you will get slides by slides link in description...Anyway,happy to be learning....😃

Harshitha Yendapally yup,i think this is the best from the basics...I loved it...

colloredbrothers This is due to process variation effects. Cells are of different size and strength as manufacturing is imperfect. Simplifying a bit: Some cells can inherently store less charge than others (due to a small capacitor size) and some cells are inherently more prone to leaking faster (due to a weak transistor). A combination of less charge (small capacitor) and fast leakage (leaky transistor) leads to a fast-leaking cell. For more, see references [8, 21, 25] here: users.ece.cmu.edu/~omutlu/pub/raidr-dram-refresh_isca12.pdf and take a look at this paper that explains the charge storage and its effects on latency: users.ece.cmu.edu/~omutlu/pub/adaptive-latency-dram_hpca15.pdf

Carnegie Mellon Computer Architecture Thank you for the response and these video's! Very interesting.

+Carnegie Mellon Computer Architecture Wouldn't the access pattern (of the DRAM) influence the need for refresh more than PVT variations? Say a particular row is constantly written to - this row would not need regular stand-alone refreshes since the write action itself inherently refreshes data. I can think of similar analogies for read actions as well, influencing how regularly refreshing is needed for a particular row that is constantly read from. But I do believe that exploiting PVT variations can cause significant gains since I think memory is designed with a significantly larger guardband in comparison to logic thereby allowing more room for adaptively cutting into the guardband and extracting better energy/performance.

+Gokul Subramanian "More than" is very debatable. However, access pattern of course affects the need for refreshing a row. The example you gave for reads and writes makes sense. In fact, take a look at this "Smart Refresh" paper that proposes to exploit the fact that a recently accessed row does not need to be refreshed: dl.acm.org/citation.cfm?id=1331714. Usually, techniques to eliminate refreshes of recently accessed rows comes at a high hardware overhead needed to keep track of recently accessed rows, however, as explained in Section 4.2 here: users.ece.cmu.edu/~omutlu/pub/raidr-dram-refresh_isca12.pdf.

+Gokul Subramanian You are right that there is a large guardband in refresh and timing. Current DRAM refresh and timing parameters are set to ensure correct operation in worst-case devices and operating conditions. Exploiting the retention time and access latency heterogeneity of different rows and operating conditions can greatly improve the performance and power consumption of modern memories. I would recommend anyone interested in this topic (retention time and timing variations in modern DRAM) to read the following papers. "RAIDR: Retention-Aware Intelligent DRAM Refresh" users.ece.cmu.edu/~omutlu/pub/raidr-dram-refresh_isca12.pdf "An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms" users.ece.cmu.edu/~omutlu/pub/dram-retention-time-characterization_isca13.pdf "Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case" users.ece.cmu.edu/~omutlu/pub/adaptive-latency-dram_hpca15.pdf You can find the presentations of these papers at users.ece.cmu.edu/~omutlu/projects.htm.

That's because there are slides from the lecture in the description

here www.archive.ece.cmu.edu/~ece447/s15/doku.php you can find all course related materials, in the prerequisites you'll find the list of related courses

Potentially, but that solution is not only too expensive (a row buffer is huge), but couples the DRAM chip design (which contains the row buffers) to the number of cores (which is part of the CPU, GPU or accelerators). So, it is not a good solution.

@@CMUCompArchThank you for your answer.

Hey, did you keep up with these lectures?

Yep digital logic combinational and sequential

2015 lectures are more recent and the recordings are likely to be better. So, they are more recommended. You can also check out more up-to-date versions of the course at @OnurMutluLectures Digital Design and Computer Architecture course from Spring 2020: kzfaq.info/get/bejne/d7ByoKySutTJcmQ.html Advanced Computer Architecture course from Fall 2020: kzfaq.info/get/bejne/mZmdg8eLppOqnZc.html

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