Please explain why we don't have quantum computers with Ning Li's room temperature superconductor?

@Anastasi In Tech - What about using i-squared-l logic and/or vacuum channel FETs, possibly on chiplets? I2L seemed very promising when first introduced, but it's power consumption was high since transistors were all large at that time. As a bipolar technology it will not suffer from gate leakage problems. Are there any other reasons why it might not work? As for "vacuum" channel FETs, they are 10 times faster or more, partly because they use free electrons. They also benefit from nanoscale features, are extremely radiation resistant, and they can operate comfortably at temperatures up to hundreds of degrees Celsius. Also they don't actually require vacuum when built at small nanoscales.

@@YodaWhat This is about Anastasi's Asus Vivobook commercial she boldly snuck into her main content?

@@fluiditynz - I left my comments and questioon here because it is the most likely place for her to see it. Nothing to do with the laptop she's promoting.

xoxooxoxoxooxox

You are absolutely right. Once I participated in a service job to get a power station running. The problem was to bring the gas engines up and running as fast as possible. After a few days the programmer had been flown in and looked for alternative assembler commands to save a clock cycle here and a clock cycle there.😁

Wirth's Corollary to Moore's Law: Any improvement in Hardware performance will be negated by code bloat at an equivalent rate. Kinda like traffic in London.

It's not a false economy, just a different emphasize due to the change in price structure. In the old days, memory were expensive, so we tried to economize its use. Today's memory are so cheap, that software developing time has become the most expensive part of a system.

@@gorilladisco9108 the cost of memory is largely immaterial. It’s the cost of execution time. Say you’ve got a transaction that currently takes 10 minutes to complete but if the code was optimised would take 7 minutes. To optimise the code would take the developer an extra 5 days effort and the developer earns £30 an hour (that’s the mid-point for a developer where I work), so that’s about £1100 wage cost but once it’s done that cost is done. Once rolled out the application is used by 200 people paid £16 an hour (I have some specific applications we use in mind here). Saving 3 minutes per transaction means either those same staff can process 30% more transactions or we can lose 60 staff at a saving of just over £7000 a day. That extra development time would repay in a little over an hour on the first day and after that would be pure cost saving.

NO COPILOT! NO RECALL! This future is PRISONPLANET!

👍🏽💚🌴☀️🌏

Has datsbus ended?

@@Raphy_Afk 😂😅no..my English is bad🐪☀️

@Magastz love💚and peace 🌏

Not bad on the eyes either

I didn't even know she was from the field, I thought she was just smart. But I guess that makes sense

- I wonder if they run veins of metal in between the layers to send the heat to radiator. - They put L3 cache on the second layer, which by virtue is quite removed from the logic circuits.

Heat, latency, voltage regulation, signal integrity, etc…. Stacked dies has never been simple which is why there aren’t many of them.

Yup! Also, a shortage of railways.

А потом ещё уйти в 4 измерение:D

It is good enough for cache application but very bad for register memory.

It also involves a physical change to the medium, which means wear and limited number of writes. I believe a similar principle has been around since at least the 90s. I used to have a CD-R/W type device that used a laser to heat up spots of a special metallic medium, changing it from smooth to amorphous. Could be rewritten some number of times. I will say though, your point is probably good and valid, but could have been made more constructively.

@@kazedcat its not good enough for cache, modern caches are at most in the low dozen of ns, 40ns is DRAM levels of latency

This is true. PCM is totally useless as SRAM replacement and doesn’t have sufficient speed or rewrite resilience. Honestly, she really failed to understand its use case. It’s a great alternative to floating-gate FLASH memory, not SRAM!

what about 4ds memory? 4.7 nanosecond write speeds

Not exactly. DRAM consumes power all the time, because it needs constant refresh to preserve contents. SRAM only consumes power during state change. Both consume some leakage current though, and with that, SRAM consumes more due to having more transistors per bit cell. DRAM also consumes considerable current to change state, because of its larger gate capacitance. Overall, DRAM tends to consume more power per bit but costs less and is more compact, which is why we use it for main memory and reserve SRAM for cache and internal registers.

I bought a book on how to improve my memory. But I forgot where I put it.

😂😂😂

@@ALTERRAa8 Alterra, also included in a game I enjoyed for a very long time. SubNautica. Thanks for the extra smiles. On my face that is.

My memory is fine. Only problem is having the parity bit in a Schrödinger box.

@taurniloronar1516 damned light. Kick the box and listen for giggles. Good one.

Not really, the silicon lattice constant is only 0.7 nanometers. We can't scale in silicon below that. Germanium has a lattice constant of about 0.5. While process nodes and technology are mostly marketing terms and there is room for improvement beyond "1 nanometer process" - we are about at the end of what we can achieve with existing semiconductor paradigms. It will be almost all architecture and material sciences by 2030. We can't get much smaller. A 20% improvement over SRAM is disruptive even if it doesn't scale any smaller. SRAM is unable to be scaled any smaller due to the physics underwriting operation. We only have a few more die shrinks left before we are up against the size of the atom. ... Again, sort of ... A 1 nanometer node doesn't necessarily mean that you can make a grid of 1 nanometer square pads separated by 1 nanometer troughs on all sides, or vice-versa. But as I mentioned, the lattice constant of silicon is 0.7 nanometers, their latest process node is 1.4 nanometers. You can't really cleave off half a crystalline arrangement without having weird things happen, the next die shrink, if it is possible, would come at 0.7 nanometers. We would be, assuming we can make the grid arrangement described, making the smallest transistors possible with silicon, using existing paradigms.... And whatever paradigm comes next would need to use atoms much more efficiently - or some other concepts entirely - to function. On the plus side, it means that in about another 10 years, we might see computers built with the idea they could last decades in their application.

@@Aim54Delta Great points! Thank you for expanding on the technological limits of the underlying physics not covered in the video. Given these fundamental limits to silicon, research efforts will move to entirely different concepts that may or may not work. Perhaps we will not see much further progress ending the decades long run of ever increasing chip performance or something new will make current silicon architectures obsolete. Fascinating field with huge commercial risk/rewards for company boards to ponder. Thank you for your comments.

I am shocked she failed to mention optane as well - "new technology" lol.

had they holded on till CXL was here imo it could have taken off, it had great promise it was just in the wrong interfaces

I thank you for your service. When intel announced that they were ending optane, I bought 6 of those PCIE drives; I caught a fire sale. Those drives are the fastest drives I have for doing some disk intensive Studio work. I wish they could've gotten the price down around $100-$200 dollars for the good stuff. I actually got 6 optanes for $45 a piece. I lucked up and bought a box.

Astro blocks.

@Sven_Dongle Was that you!? I though it was David! Good job 👍😉😆 I enjoy your work.

Yups.. but it keeps bulking

Not bad. My kid at 2 would stack boxes to make a stair to get over the gate. Necessity is the mother of inventions.

Oh hey Al gore… when did u change your name? Lol

So basically smart RAM chips with shaders?

telegram probably if shes russian

NO COPILOT! NO RECALL! This future is PRISONPLANET! NO WORK NON-STOP!

Thank you for being here

optane's real problem was it being place in 2 places where it didn't belong, one was a flash competitor which placed it in a much too slow interface, another was in DIMM competing with much faster Dram chips, if we make a dedicated space for it optane could really bring some benefit but we need to do it the right way.

Heat exchange maybe?

Yes, though theres more limitations, it's really hard to manage heat in a 3d structure. It also requires new innovative ways to do it. This is why a room temperature super conductor would be such an amazing breakthrough. You wouldn't need to worry about heat management and you could up the frequency to Thz levels while maintaining manageability even in a 3d transistor structure. Computing would be millions and billions and even trillions of times faster

There are different kinds of resistive RAM. Memristor is just one of them.