Silicon Photonics Chiplet Package - Optical Assembly
Chong Zhang
Ayar Labs, Inc
This presentation provides an overview of the packaging technologies for silicon photonics chiplets, with a focus on the in-package optical components and optical assembly processes. To meet the demands of future high-performance computing, in-package optical I/O chiplets are essential due to their high bandwidth, low energy consumption, low latency, and long reach capabilities. The presentation covers the packaging process flow of TeraPHY™ optical I/O chiplet and describes the electrical and optical architecture of a silicon photonics package module, while acknowledging the need for further development of the optical assembly ecosystem, which is still in its early phase. The presentation also addresses the requirement for 2nd level optical interfaces and the need for a new industry standard. Multiple options for first-level optical interfaces on silicon photonics chips are analyzed and compared. Finally, this presentation assesses the requirements for optical fiber, optical adhesive, and optical assembly equipment for silicon photonics chiplets.