Power Plane as a Return Path | Signal Integrity

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Күн бұрын

What happens when you route over a power plane and use it as your reference? And what happens to a return current when its return path is over a ground plane? Tech Consultant Zach Peterson dives into these questions and more in this exploration of using a power plane as a return path.
0:00 Intro
0:37 Return and Displacement Current
2:18 Ground Vs. Power Plane
4:56 Method One: Capacitors!
8:22 Method Two: Reconfigure the Stackup
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Пікірлер: 59

@CARlosDAN783 7 ай бұрын

My dear engineer Zach, I am addicted to all your videos, I want to stop watching them but I can't :-) since each one is too interesting. Thank you and a big hug from my withered 🥀 Venezuela.

@Zachariah-Peterson 7 ай бұрын

Thank you very much for watching!

@m4l490n 2 жыл бұрын

Excellent! Thanks for clarifying why having a power plane in a 4-layer board is not a good idea. It is too much trouble and prone to issues. It is especially bad when routing a signal from one side of the board to the other which would mean changing reference planes from pwr to gnd. It is not necessary to have power planes for circuits that and and would be done in a 4-layer board. Power can always be routed in these. If you need plane capacitance that means your design should probably not be on a 4-layer board anyway. It is always better to have SIG/PWR-GND--GND-SIG or GND-SIG/PWR--SIG-GND in 4-layer board stackups. Absolutely any microcontroller-mixed-signal design can be done with this stackup having routed power only, no power planes, and two GND exclusive planes.

@rahuls7039 2 жыл бұрын

Mr. Zach, you are the best. Learnt a lot from you and still learning. Thank You and have a great holiday ahead...

@AltiumAcademy 2 жыл бұрын

Same to you!

@Zachariah-Peterson 2 жыл бұрын

Thank you very much

@dmitry.shpakov 2 жыл бұрын

Thats informative. Thanks Zach!

@jayashripattar7626 3 ай бұрын

I really liked the way you follow to explain the concepts in all your vedios, thanks a lot

@user-gp1do4of2x 4 ай бұрын

Excellent stuff! 🙂

@asmi06 2 жыл бұрын

The problem with the last solution is that such non-symmetrical stackup can cause pcb warping after reflow if the board is large enough. I had this problem with 20x13 cm 4 layer PCB, so that's definitely something to keep in mind.

@Zachariah-Peterson 2 жыл бұрын

That's a good point, although I have had fabricators tell me to not worry about this in certain stackups, especially if the board is small. 20 cm is relatively large (8 inches), so yeah warping would be a consideration, whereas we've done this in a small 2 in by 3 in board and warping was not a problem. You could always fill in that top layer with copper...

@saeidesekhavati1518 2 жыл бұрын

You answered me a big question! Thanks a lot!

@AltiumAcademy 2 жыл бұрын

Glad to hear it!

@Retinatronics 2 жыл бұрын

Super important topic! Thank you.

@AltiumAcademy 2 жыл бұрын

Glad you think so!

@maks886 2 жыл бұрын

Fantastic!

@DiegoColl44 2 жыл бұрын

Great, good topic. Thank you.

@AltiumAcademy 2 жыл бұрын

Glad you liked it!

@maritzaarevalo7835 Жыл бұрын

Thanks you!! You are the best!

@AltiumAcademy Жыл бұрын

You're welcome!

@BeMuslimOnly 2 жыл бұрын

Thank you. It was useful

@AltiumAcademy 2 жыл бұрын

Glad it was helpful!

@Parvi_ 2 жыл бұрын

As always, a very informative video in such a short time. Thank you so much! Questions please: 1# What if we route a signal over a power plane of differnt voltage level? eg; A 1.8V CLK signal over a 3.3V power plane or 3.3V CLK signal over a 1.8V power plane. 2# How rise/fall of 3.3V signal line will cause a displacement current if both signal and plane are at same potential and in what direction the displacement current will be the considering higher and lower potential side.

@Zachariah-Peterson 2 жыл бұрын

Hey Raza, #1 In terms of the return current, the only thing that changes is the polarity of displacement currents. At some point, the ground has to source or sink some charge into the PDN depending on reference voltage compared to signal voltage. #2 The displacement current is a transient response, meaning it is excited when something changes. In this case, it is the signal level that is switching between two values. This is essentially the same idea as in #1, the polarity may be different in the power plane, but that will cause a displacement current to also appear in the power plane, which is coupled capacitively.

@Parvi_ 2 жыл бұрын

Hi, thanks for the detailed response. #1 So, that means during a rise time of a 1.8V signal line that has a reference plane of 3.3V below, the displacement return current will flow from the power plane into the signal line?

@mata7648 2 жыл бұрын

If I have a virtual ground plane, what is a good stackup for a six-layer board? For example, a 5V power rail and 2.5V virtual ground.

@jeremyglover5541 Жыл бұрын

Thanks again Zach. I thought I remembered this video existed and had to search back to check. i'm laying out a trinamic stepper motor driver at the moment, so me and mixed signal again ... the eval board for the part specifies 4 layers with layer 3 being power and the gate drive traces and output polygons on the bottom layer ... this got my attention; I started laying out the board and sure enough thats one of the neater ways to route the pinout with their chip without traces crossing over, but it made me uneasy. their eval doesnt have anything at all to deal with transfer current ... I guess because its not really a product that has to pass regulations, but I still just thought I would rework it. making it 6 layers is not an option, so my options are swapping layer 3 and 4 and routing the gate drive traces on a power layer on the bottom, with sig/power, Gnd , Gnd , sig/power, or just going with routed power. I think i'll go with the latter.

@Zachariah-Peterson 11 ай бұрын

Yes that sig+pwr approach works for a lot of designs, including the type you're working on, but if you just have power routed on the back it ends up being the same for a lot of designs. One thing to remember about eval boards, those designs never consider what else you might have in your custom design, which could be a lot of interesting stuff (MCU, ASICs, etc.) so their stackups might not always work for other designs.

@jeremyglover5541 11 ай бұрын

@@Zachariah-Peterson yes, im starting to notice that more and more. Designed to meet headline specs in isolation. The switching node and its role thermally dictates a change of tack. There is only so much copper you can put on the extended top source pad/pour copper and expect it to spread across the plane, so the arrangement of the node underneath, where it becomes the output polygon, as well as the interface to the heatsink. Normally the sort of surface area you would want to restrict for stability, but not when you want to transport heat as much as you can with limited area. Quite a challenging little thought experiment.

@Zachariah-Peterson 11 ай бұрын

@jeremyglover5541 Exactly about the headline specs, Heidi Barnes was saying this in our podcast last year specifically with respect to power regulator boards that use a ferrite in the output filter stage; those boards are usually meant only to handle DC loads, but then people wonder why they get too much high frequency noise on a power rail when they use the same circuit to power a large digital processor!

@jeremyglover5541 11 ай бұрын

@@Zachariah-Peterson ha!! yes, I would expect RFI performance similar to a planar antenna.

@user-ww2lc1yo9c Жыл бұрын

Capacitors have ESL, at high frequencies components it can have a large impedance, the via path from plane to capacitor also has inductance. So, how well will this work when we expect the signal currents to go through the capacitor from PWR plane to GND plane?

@nurhaida1983 5 ай бұрын

Hey Zach, thank you very much for this video! I'm just curious, would via fence help for long traces' return current where the via fence are implemented along the trace at the region where the capacitors are not placed (as you mentioned in the video) if I can't change the 4-layer stackup of Signal, PWR, GND, Signal? Thanks again the video!

@Zachariah-Peterson 4 ай бұрын

Thanks for watching, a via fence will not help in that regard if placed along a trace, but you could use some copper pour around the high-speed traces. If that copper pour is grounded it will provide a return path, including if you route over any splits in your power plane (such as if you have multiple power rails).

@xenofontzaras2741 Жыл бұрын

Hello Zach, So actually you tell, if I have a signal on top, it induces some displacement current to Layer below, (that is Power in that case), and then, this displacement current continues to GND layer trough the discrete decoupling capacitors that are hopefully distributed somewhere near (Video 3:30)? I have some questions: - So am I wrong here to say, there are two kind of currents, displacement current that goes through dielectric, and the "normal" current that goes all the way down to the receiver input? - How much is this displacement current for a typical digital signal , compared to the whole current ? I know about rise time, etc, but is unclear, when it becomes a serious factor, and when I just can ignore this problem - Your are mentioning, the capacitive impedance between Top and Power Layer is much less compared to the capacitive impedance between Power layer and GND Layer, but why? There should not be a big difference, dielectric thicknesses should be more less the same, or not? In our board, it is the same for all layers, except core maybe In ca 7th minute of your video, you are mentioning the two caps connected on each chip from power to GND, they provide a good impedance path for the signal So here you are still describing the return path for the displacement current ( only)? kind regards Xenofon

@Zachariah-Peterson Жыл бұрын

There are a few things to address here... 1) When we say displacement current, we're referring to current that is induced on a conductor through accumulation of charge on a separate conductor when the two are not in physical contact. This is mediated by the Coulomb force, or at least that is how we look at it from the electrostatics point of view. In terms of the insulator between the trace and the plane, the displacement current is related to polarization of the medium separating the two conductors as this will determine the dielectric constant of the insulator. 2) When the signal is propagating along the trace, the current is changing over time, so at any instant there will not be constant current somewhere on the trace. The displacement current due to capacitance is I = C(dV/dt), so take the trace capacitance in the region where the signal is rising/falling and use the voltage change rate to calculate the current. 3) The capacitive impedance between the power layer and the ground layer is not always smaller than the capacitive impedance between the trace and ground, but it can be smaller depending on the overlapping area between the planes and the dielectric thickness between the planes. The dielectric thicknesses are not always the same. For a signal, you have some capacitance per unit length, and depending on the length/width of the route and the board size the two impedances could be comparable.

@celalkavlak454 6 ай бұрын

Thank you for the informative video. In the first configuration, why does not displacement current complete the loop through signal trace-> PWR plane-> PWR via of IC -> PWR pin of IC -> signal pin of IC? because I thought the source of displacement current is IC and it is returned to source with minimum impedance in this way instead of completing the loop through GND plane. Total of return current from receiver->GND plane->decoupling capacitor and displacement current from PWR plane will be equal to signal current at signal pin of IC? Best regards.

@Zachariah-Peterson 6 ай бұрын

In the first configuration, your description would require conventional current moving backwards under a positive voltage, which by definition cannot happen. The movement through the ground plane is minimum impedance at very high frequencies, while radiation away from the board is the path of minimum impedance at lower frequencies. Regardless of the return path, the displacement return current would be the same as you state.

@malamian1 2 жыл бұрын

Thanks for the helpful content. How about using this stackup: L1:Gnd L2:sig/pwr L3:sig/pwr ang L4:Gnd?

@Swasan2112 2 жыл бұрын

There will be coupling between L2 and L3 layers... So no good

@Zachariah-Peterson 2 жыл бұрын

We discussed this one in an earlier video, here's the link: kzfaq.info/get/bejne/mJqeltZp1sylmXU.html. This one can work but it depends on how it's routed. If you keep signals on the adjacent sig/pwr layers separated from each other then you can prevent crosstalk between signals in those layers. Madeti is right though, if not routed properly you could have coupling between those layers.

@dhrutiranjangaan5273 Жыл бұрын

For high current multiple switching lines, whether return should be through traces or through a ground plane?

@Zachariah-Peterson Жыл бұрын

I would do it through a ground plane for multiple reasons. You will have lower noise, especially when you consider the fields being generated at high switching rates, and the copper will act as a heat sink for any components operating with high power dissipation.

@2LukeLOL 2 жыл бұрын

Interesting! It seems like almost all signal inegrity problems on a PCB are solved by ensuring there is a continous GND plane either above or below each signal/power layer. Although this raises the question, is it not standard practice to always ensure there is always a continous ground plane above or below all signal planes? I thought this would be common practice for designers

@Zachariah-Peterson 2 жыл бұрын

Well yeah it should be common practice for designers, but you would be surprised how often it gets intentionally omitted because the designer doesn't want to spring an extra $10 per board for 2 additional plane layers. For low-power, low-frequency stuff that doesn't need isolation and that has a lot of grounded copper pour, you might be able to get away without a ground plane in a 2 layer board in terms of EMC/EMI because now you're not using it for something like impedance control or for maintaining tight return paths. I would say that ground planes help solve the most basic signal integrity problems that are present in most digital boards, even at lower edge rates.

@setia2258 4 ай бұрын

Hi Zach, what do you think about pouring layer 4 with GND if we have SIG-GND- PWR-SIG?

@Zachariah-Peterson 4 ай бұрын

Good question, I have seen this come up a lot lately and I will be doing a video about this stackup. We also saw this in one of the 1 minute design review shorts so I think it is worth covering in a longer video.

@setia2258 24 күн бұрын

@@Zachariah-Peterson Thank you.

@setia2258 24 күн бұрын

@@Zachariah-Peterson anyway, sometime we made SIG-GND-GND/PWR-SIG, what do you think? Is that better than SIG-GND-PWR-SIG, since we combine layer 3 with GND and Power. Thank you

@Zachariah-Peterson 23 күн бұрын

@@setia2258 I think SIG-GND-GND/PWR-SIG is better than SIG-GND-PWR-SIG

@setia2258 8 күн бұрын

@@Zachariah-Peterson Got it, Thank you

@pravinsengottaiyan9244 2 жыл бұрын

Can you Please...🙏 Kindly teach how to review the layout.if you did already videos.please kindly share the links.it will helpful for my life. Thanks

@Zachariah-Peterson 2 жыл бұрын

Sure that sounds like a good topic, I'll look at some example projects we could use and we'll get this into our video queue.

@pravinsengottaiyan9244 2 жыл бұрын

@@Zachariah-Peterson Thanks a lot

@unwatchable. 2 жыл бұрын

what about splitting a power plane to power+ ground plane. and keep ground copper on plane under the high speed routes. ???

@DDas-yi6jr 2 жыл бұрын

Yep, good question

@Zachariah-Peterson 2 жыл бұрын

That is possible but I don't see the benefit of splitting a power plane to power + ground and then routing over the split arrangement. The problem is you'll start routing over a gap and you would have to line up a bunch of caps across the split so that you can keep a return path back to the GND side. The other solution to that split problem is to place a GND plane below that split layer, but then you get back to the potential problem of tracking return paths back to GND through capacitive coupling. One exception I will tell you is in large backplanes that we have done as these boards were running high current and digital signals with bandwidths reaching 85 GHz in the same board and on the same layer, so we needed as much isolation and copper as possible, and then we just route everything over the GND as you suggest. This was possible because the boards are so physically large. I've done it in smaller MCU boards, but those boards were running at lower speeds and we used copper fill to stitch together all the grounds and provide return paths everywhere.

@rutwijmulye6381 2 жыл бұрын

When it comes to selection value of De-cap...the De-cap value should be greater than capacitance between PWR and GND?!....is there any specific constant for selecting Decap value?