Razavi Electronics2 Lec15: High-Gain Differential Pairs, Intro. to Diff. Pair with Active Load

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Behzad Razavi (Long Kong)

5 жыл бұрын

Пікірлер: 36

@rahulchatterjee4177 5 жыл бұрын

Arguably the greatest teacher of electronics

@rahultheytv5347 4 жыл бұрын

Thank you sir ,,, its very rare to find people sharing information with caring and no cost minds

@bitvision-lg9cl 10 ай бұрын

Thank you sir, I understand what’s the potential means from this lecturer.

@coolwinder 3 жыл бұрын

01:26 - Intro 04:00 - Differential Pair with Ideal Current Source Load 09:20 - Cascode Differential Pair 15:30 - Telescopic Differential Cascode Pair 23:37 - Cascode Differential Pair with Active Load

@enesog 4 жыл бұрын

At 33:02, if you cant see the green writing, make a snapshot, put it in paint and reverse the Colors, so you can see it easy.

@deepdivdivdeep 5 жыл бұрын

Thank you very much for the precious teaching from sir.

@amitgalkin1215 2 ай бұрын

best teacher! great insights!

@qawasmi1992 5 жыл бұрын

Razavi the Great

@juelzpole1783 4 жыл бұрын

So kiiiind. Thank you

@user-zl7ql6xz5y 2 жыл бұрын

Really thank you .

@mnada72 3 жыл бұрын

Waiting eagerly for circuit theory I & II and the rest of the series.

@vimalkantpandey 5 жыл бұрын

Thank you very much. When you are going to upload other videos of this series like Lecture 14 and others

@varaprasadgrandhi8101 4 жыл бұрын

Sir what is the difference between the regisitive load and current load. Because they are having same representation in mos diagrams.

@vaisnavashok930 4 жыл бұрын

Why are the videos having an abrupt ending?

@HardikJain_YT 4 ай бұрын

42:32 beautiful

@vigneshrshankar668 Жыл бұрын

It has a name.. If you don't like the name, don't worry about it ! :D

@devikaramesh1143 Жыл бұрын

😂😂

@askago4884 3 жыл бұрын

Make me strong you sir ........

@oakspines7171 Жыл бұрын

We use active load instead of passive resistor.

@brucemuller9205 6 ай бұрын

In differential pair with active load , when ID1 increases, ID3 increases, so ID4 increases due to mirroring...but ID1+ID2 = Iss which is constant...and ID2=ID4 so by this logic ID4 should decrease when ID1 increases. Does it mean that M4 is in triode region?

@sandeepmaurya5133 5 жыл бұрын

Sir please do not use green color,it is not clear though.

@saisumanthnatva3560 4 жыл бұрын

At 7:53, ideal current source should be replaced by a resistance (internal resistance of a mosfet, let's say ro3). So, gain will be -gm(ro1 ll ro3). Isn't it?

@mazensayed3250 4 жыл бұрын

it's called "ideal" because it doesn't have channel length modulation effect (ro)

@dhirajkumarsahu999 4 жыл бұрын

an ideal current source is a one, whose current always remains constant. That's why, while drawing the small-signal model, we replace it with an open circuit. (while drawing the small-signal models, we only consider small changes)

@AllenSA_airohaSun Ай бұрын

CLM=0 and it means that ro infinity So Adm=-gmRd Otherwise the CLM is not equal 0 and it means that hava a ro Adm=-gm(Rd//ro) rds= ro=va/id=(1/CLM)/id=1/(id*CLM)

@mrpossible5696 5 жыл бұрын

43:10

@amitkumar-sh2lk 4 жыл бұрын

Sir please dont use light green colour for writing as it is not visible . istead u can use dark green colour

@shikharsrivastava8346 4 жыл бұрын

42:24 please xplain,i didnt understand the 2 case

@zaki5726 4 жыл бұрын

in the second case consider the nmos to be a resistor if an increase current has to flow through the nmos then the potential drop across it will be higher , hence v out will be higher

@abhishektyagi7513 4 жыл бұрын

@@zaki5726 I agree but think like this, to maintain the nmos in saturation Vds>Vgs-Vt. In the first case, Vgs of the lower nmos is rising as more current has to be pushed through due to current mirror action. If Vgs increases, then so should Vds to maintain the pinch off condition. This is opposite to what I will get if I consider the loading mos as a resistor where a current increase will just give a greater potential drop across it and thus Vout will drop. I am confused. Can someone explain where I am going wrong?

@dhirajkumarsahu999 4 жыл бұрын

@@abhishektyagi7513 if the Vgs of the lower nmos rises (which rises due to more current due to the action of the current mirror), it does not imply that the Vds should also increase. In fact, with the increase of voltage between the gate and source, the voltage between the drain and source decreases. That's why it acts as an inverter. You would also have observed, its gain is given =-gmRd( negative sign indicates inverted output). This can be explained as follows- as the voltage at the gate increases, the channel gets more enhanced with the charge carriers. This results in decreased resistance of the channel, and hence the Vds decreases. I hope this will clear your doubt.

@shubhamnayak9369 4 жыл бұрын

@@dhirajkumarsahu999 but you see.. when I increases, Vgs of Ma increases so Vgs of Mb also increases and as Mb is CS stage so Vo should decrease. But here it's something else is explained

@kunalvatwani9535 2 жыл бұрын

So basically m1 wants id1 to increase which increases id2 so Vout increases And M2 wants to decrease id2 so that Vout increases. id2 both increases and decreases and in both cases increases Vout?????? Something seems wrong

@Priyajit_Ghosh 11 ай бұрын

I think superposition is taken here. 1. Vgs of M2 dec -> Im2 dec -> now think M4 as a resistor, -> Vdd - IdRd = Vout - > Vout inc 2. Vgs of M1 inc -> Im3 and Im4 inc-> think M2 as a resistor -> Vout = IdRd -> Vout Inc