Modern products are packed with serial links, yet many engineering teams don’t have an effective strategy in place to verify SerDes-based serial links after routing. Electronics designs are becoming so complex and dense that automated verification is the only cost-effective solution.
This video shows how HyperLynx can automate post-layout verification of hundreds of serial links overnight. You’ll see how HyperLynx uses a progressive verification methodology that starts with running an electrical design rule check during PCB layout, then utilizes protocol-specific compliance analysis to look at the system level interconnect. Finally, see how HyperLynx uses IBIS-AMI model simulation to predict how the system will perform with actual devices and settings.
HyperLynx provides a SerDes post-layout verification flow that allows PCB and hardware designers to identify potential problems early, without needing to draw down the scarce resource of a signal integrity expert. Ensuring serial link compliance is easier with HyperLynx!
▶️ Chapters:
0:10 How do you verify your serial channels before prototype fab?
0:59 The HyperLynx post-route serial link verification methodology
2:06 A look at the board that will be used in this demonstration, which has 336 serial channels
2:50 Electrical design rule checks
4:47 SerDes protocol compliance analysis
6:34 Large-scale simulation results
8:10 Post-layout analysis coverage
9:20 Identifying critical areas for 3D modeling
10:46 Running large simulation jobs with one laptop
11:24 3D simulation results for 336 channels
12:26 Quick stackup study
13:00 Would this really find a problem?
13:36 IBIS-AMI simulation
14:32 Summary of post-layout serial link verification
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