Systemverilog Assertions: S3 - Immediate Assertions & Concurrent Assertions

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Systemverilog Assertions: S3 - Immediate Assertions & Concurrent Assertions

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Difference between Immediate and Concurrent Assertions in Systemverilog.
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Пікірлер: 14

@kumardivij8008

@kumardivij8008 3 жыл бұрын

At 8:53 "assert property @(posedge clk) !(wr_en & rd_en);" throws an error for the xcelium simulators during compilation. An extra parenthesis is required for the expression after "property". "assert property ( @(posedge clk) !(wr_en & rd_en) );" solves the compilation error!

@SystemverilogAcademy

@SystemverilogAcademy 3 жыл бұрын

You are right, its there in the LRM and I typed it wrong. Some simulators might not complain, but we should always do as per LRM. Thanks Kumar for this correction.

@jaredalfredvelasco7812

@jaredalfredvelasco7812 2 жыл бұрын

finally a good video on SVA

@SystemverilogAcademy

@SystemverilogAcademy 2 жыл бұрын

Thanks for the feedback 🙂

@lintomonful 3 жыл бұрын

Ajith,Good presentation :)

@SystemverilogAcademy

@SystemverilogAcademy 3 жыл бұрын

Thanks 🙂

@dushyanthgala9122

@dushyanthgala9122 2 жыл бұрын

good explanation

@SystemverilogAcademy

@SystemverilogAcademy 2 жыл бұрын

Thanks for the feedback 🙂

@uday5786 4 жыл бұрын

Please share the ppt

@SystemverilogAcademy

@SystemverilogAcademy 4 жыл бұрын

Sorry, it can't be shared.

@StayInBliss 4 жыл бұрын

like the things

@SystemverilogAcademy

@SystemverilogAcademy 4 жыл бұрын

Thanks!

@dushyanthgala9122

@dushyanthgala9122 2 жыл бұрын

okay

@SystemverilogAcademy

@SystemverilogAcademy 2 жыл бұрын

👍

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