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Systemverilog generate : Where to use generate statement in Verilog & Systemverilog
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@SandeepKumar-px4kf Жыл бұрын
very good explanation
@ravisoni9645 3 жыл бұрын
Very simple explanation,Thank you so much for your hard work,keep posting more such videos. Thanks alot
@SystemverilogAcademy 3 жыл бұрын
Thank you for the feedback !
@lakshmikanthk442 3 жыл бұрын
Can we use generate block inside the functions, like if we have recursive call?
@SystemverilogAcademy 3 жыл бұрын
I don't think there is any restriction for the usage of 'generate' inside the function, but always be aware of the use case of 'generate'.
@tanujsharma6316 3 жыл бұрын
can there be nested generate statements? if yes then what will be the name for the instantiated module
@SystemverilogAcademy 3 жыл бұрын
It's possible according to the LRM. (Refer "27. Generate constructs" in the 2017 LRM) The instance names will also appear accordingly. Example, parameter SIZE1,SIZE2 = 2; genvar i, j generate for (i=0; i
@harsha9215 2 жыл бұрын
sir, Does modules in generate block will execute concurrently or sequentially? if concurrently how to use generate for interdependent modules.
@SystemverilogAcademy 2 жыл бұрын
If you 'generate' any block of code (including module), they will be executed in parallel in simulation. (didn't get your second question 😕 )
@harsha9215 2 жыл бұрын
@@SystemverilogAcademy is there any way to excute module serially
@noufalnishath1937 3 жыл бұрын
hi, i have tried the same scenario without providing generate block.but still getting output without any error.could please explain me why?
@SystemverilogAcademy 3 жыл бұрын
If you don't use generate, it will not 'generate' multiple components , it will be just a single circuit component.
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