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Great for verification, formal methods can also supercharge hardware development. In this quick tutorial overview, I'll provide key highlights from my recent talk at the Free Silicon Conference (FSiC2023) focusing on the tools and techniques I use while creating FPGA and ASIC designs: namely cover and BMC.
Cover statements are useful to see the system in action, to do simulations without micromanaging every single signal, and even to find solutions to problems.
Bounded model checks are great for hunting bugs but I also show a neat way to use BMC to do sneak path analysis.
The full "Black-tie Python: Formal verification with Amaranth" talk is available at:
peertube.f-si.org/videos/watc...
Details about the conference may be found at:
wiki.f-si.org/index.php?title...
All the other talks are also online at:
peertube.f-si.org/video-chann...
and they are well worth it.
Though the techniques covered here are all pretty independent of the language/toolkits you're using to implement your hardware FPGA/ASIC designs, here I'm using
Amaranth (Python):
amaranth-lang.org/docs/amaran...
Yosys/symbiyosys:
yosyshq.readthedocs.io/projec...
symbiyosys.readthedocs.io/en/...
And you can have a look at the amaranth_testbench library, which I introduced and used in much of the talk, that includes all the examples I covered and more:
github.com/psychogenic/amaran...