Can it play starfield

@@ummerfarooq5383 can Starfield play?

@@ummerfarooq5383 There is enough PCIE and RAM for 7 players to each have the P-cores of a 12900K and their own full bandwidth 4090.

@@DigitalJedi thanks for you insight, always nice to see engineers talk about the work they do ;) I'm busy playing Starfield and porting it to my C128, why because I think that Z-80 will work as a nice co-processor to the 8510 CPU, ha :p

any special reason why there's an asymmetric 3+2 bridges instead of having 3 on both sides?

💀💀 the cooling on that bad boy is gonna be insane

@@RENO_K with 3m's liquid that boils at almost 50 celcius you could maybe pack almost a thousand per rack

Yo same

@@startrekkerll5635 What do you mean? You still have memory slots that you can put memory in...

This one took a long time. Partly due to the complexity but also moving STH to Scottsdale and doing like 40 flights over the summer. I was hoping to get this live before Taiwan last week.

Bottom of what?

@@aarrondias9950 the cpu module/pcb

@@Gastell0 1:01

@@aarrondias9950ooh, that was in introduction, I looked over again everywhere but that, thanks!

Same! And it only takes like 10 minutes!

That's seriously cool

No the original Pentium III (0.25um Katmai) does not have on die L2. It only comes in the 0.18um Coppermine version, which was super cool. The 500Mhz coppermine can OC to 666MHz without a sweat.

Ever heard of M-series macs?

Exactly my thought.

HBM gets wiped as any other memory on power loss. It has nothing to do with Optane and persistent memory

@@TheExard3k It's not about persistency. But when your persistent storage is so fast and low latency as Optane was supposed to be you can get away much much smaller memory pools, hence you can use faster HBM. The entire promise behind Optane was that it is so fast (especially IOPS wise) that you don't need to keep your entire application's data in memory.

@@sehichanders7020 Well, it is a bit higher level in a sense, tiered pipelining is not _either_ HBM _OR_ Optane, correctly used both will be a boost just at a different level, Optane has been used as RAM lower tier and HBM here as higher tier, so from the CPU looking for data it would go L1, L2, HBM, RAM, Optane, mass storage if it needs to go that far with each tier being progressively slower and larger. It would work very well most likely, just be hella expensive and a bit of a bear to backend manage. But it would boost performance a lot for almost all data intensive types of applications since you'd never loose more clocks than absolutely necessary to get the needed data, so the CPU would be waiting a lot less time than it does now, which is very advantageous. Now if the data is not in L2 or L3 you have a immediate hit of 10+ clocks to check RAM and if you draw the short straw you have to go fish in mass storage SOL.

Compare it to GPU VRAM - sure top of the line GPUs have slightly more but H100 is pretty industry standard and has 80GB. Considering CPUs are definitely going to have way lower throughout than GPUs it doesn't seem like capacity would be the issue.

its a HBM2e also works like VRAM, its superfast btw my P40 24GB tesla with GDDR5 gets 2,50 sec in stable diffusion, while P100 16GB with HBM get 0,8 - 1,5 now imagine i use double P100

@@ThelemaHQ stablediffusion isn't really memory bandwidth limited. Things like, say, transformer based large language models are.

Took a little longer than expected because of a trip to Taiwan. I hope you have a great week

Similar to how L2 cache used to be external to the CPU, then moved adjacent to the CPU with the Slot 1 and Slot A, and then moved completely internal to the CPU die, gaining performance with each evolution.

if the memory fails, throw it out. This is the way now, integration of core components at the sacrifice of modularity and repairability

I don't know if this system supports it, but CPU hotplugging exists. Maybe the least useful way to do it, but that would be 1 way

I want to someone run starfield on it just for show. Of course let the cpu be overclocked to 5ghz

Amd instinct

This issue is that HBM is very expensive, and doing HBM right means a pretty much ground-up design for your chip to not only fit in the PHYs for the kilobit+ bus, but also the differences in controllers and possibly dual controllers if you still want DDR5 options. I've worked with HBM, and when you get to the class of connection density it requires, you need to spend the big bucks for a silicon interposer. Radeon Fiji did this, Vega and VII, and The Titan V come to mind. That is a whole massive die you need to make and then stack at least 2 other dies on top of. An HBM APU sounds awesome I agree, we even saw a glimmer of it with the i7 8809G, which had a 24CU Vega MGH GPU and 4GB of HBM. The more practical approach for right now though would be something with a dedicated GDDR controller, even just 128-bit 8GB would be plenty, as that is already around 288GB/s of bandwidth you aren't fighting the CPU over.

Meteor Lake has hundreds of megs of L4 cache in the interposer, presumably mostly for the iGPU and as a low-power framebuffer (somewhat like the M1).

@@DigitalJedi Yeah I know there are definite issues. HBM has a 4096 bit bus which is gigantic compared to anything else and is why you need the complex interposer. Intels EMIB looks interesting and may help in that respect but we will have to see. Personally I would not have the option for additional DDR5. This would be replacing it. Many systems already use soldered memory so this would simply be an extension of that. I would dare say 90% of consumers don't bother upgrading the RAM on their computers anyway so if it is balanced properly it wouldn't be much of an issue.

I think CXL memory in the PCIe Gen6 generation will have more bandwidth and be more interesting, but some applications will still like locally attached. More interesting is if there is optically attached memory.

Thank you

Something like that would be valuable in the consumer market I reckon. Servers are already notorious for long boot times so I don't think there is a lot of incentive at the moment to enable a fast boot.

Does AMD have a similar service? I've been wondering about the benefits of buckets of L3 cache.

@@magfal AMD doesn’t offer anything like the IDC to my knowledge. Just another edge Intel’s size and resources can deliver.

​@@magfal Supermicro has their Jumpstart remote access, they can lend you an AMD server. Bergamo was even available pre-release

This has been in production and is being installed into the Aurora supercomputer which will likely be the #1 in the world in November. Grace Superchip you cannot buy yet (we covered it on the STH main site) despite the hype.

Optane drives have failed to write endurance being exceeded. Being used as DRAM extensions IIRC. Its best placement is as a large swap space or cache for tiered storage to preserve endurance and power on time of other tiers. Intel stopped production / development and sold it due to it not selling well enough. The purchaser IIRC was a company primarily focused on memory. Enterprise and high end prosumer SSDs serve sufficiently where it fits best for a tiny fraction of the cost per cap.

Because Apple knows they have no chance in the HPC biz , Apple rules where the looks matter.

You know I was sitting in the front row when that presentation was given in Oregon back in 2017

Kind of a long time ago. Things can change in that length of time right Patrick?@@ServeTheHomeVideo

This is not unlockable from what I understand

Often supercomputer clusters. See the new Intel Aurora supercomputer as an example.

@@ServeTheHomeVideo It is amazing!! 2 billion billion calculations per second. One thing that interests me that was mentioned being done by Aurora was Dr's studying neurology and mapping out the brains neurological pathways. What does the program running that even look like and also that it needs such mind bending computational power? I know I'm in way over my head, but to me it's such awe inspiring work.

In a way, yes. But think of it more as caching slower/ higher latency/ higher trace power far DRAM to faster/ lower latency/ lower trace power close HBM. There is a big difference between access over a few mm on package and going out of the package, through the socket, through the motherboard, through the DDR5 socket, onto the DDR5 module and so forth.

It’s "3D" Stacking, that makes it much more expensive. It’s similar to HBM Packaging (but still different) and not just a couple of Dies glued together on the same package. AMD could so it but they want lower costs. AMD uses these packaging techniques but not in Ryzen/EPYC CPUs

We will have a video with Xeon Max in it later this week.

@@ServeTheHomeVideo would be nice to get some superpi, cpuz, 7zip and geekbench benchmarks for the 9480

That is powering the former #1 supercomputer: www.servethehome.com/supercomputer-fugaku-by-fujitsu-and-riken-revealed-at-no-1/

If your workload fits in the on-chip memory, why bother with additional ram?

Goes to show you there is more to these decisions than a PC benchmark. I can imagine it gets quite complex comparing all the features.

Also how much is shared with the standard SPR parts since a lot of the difference is in packaging

On a serious question what is the most powerful CPU you can get for a home PC?

good catch 😆

this chip will never see any desktop workloads. 1.14 G/core is considered unusually low even for HPC, though there are some fields that would be OK (MD, mainly). 4G/core is more like a normal HPC config, and of course enterprise is often higher, including hyperscalers. (cloud stuff may start with .5G/vcpu, but that vcpu is as little as 10% of a real core).

@@markhahn0 If I had a regular media program I'd start taking pseudo-bets on when LMG gets one. There are probably others too tempted. Someday it will be cheap as data centers dump them for new tech. That's when others will get some portion of those dumps to try them for other purposes. This chip comes with 64 GB HBM. Someone will tinker with it just as old Xeons were given new lives in gaming PCs. It would be interesting to find out how it performs and scales to keep its cores busy without DRAM, but adding a lot of it is also an option.

Everybody thinks Apple is being stingy or playing games with RAM. Memory of that type can't be slotted. Because of timing and signal propagation, the LPDDR memory has to sit close to the CPU and be soldered. Which in a way leads to HBM memory. I think that will happen and Apple might do that in the consumer or PRO space at some point.

@@billymania11 what are you even talking about. Numerous laptops and desktops have slotted RAM. Your high sleed RAM remains factory determined, as part of the SoC, and "slow" RAM can be slotted in at a later date by the user. Many computers have used Fast/Slow RAM configurations. Every modern computer already does this, to andegree, with Cache. This is merely adding one more later between. SoC fast RAM, and slower socketed RAM.

Sure Rich, whatever you say.@@richfiles

@@billymania11 i am literally describling what is inside laptops. _today..._ I work in a PC repair shop. I have been building and repairing computers most of my life. My first computer repair was in 1989. Look up how Cache memory works. Computers have had different amounts of different speed memory on and off die for decades. Most CPUs have at least 2 or 3 levels of cache memory, plus the external RAM accessed through the memory controller (also on die with modern CPUs). Some computers (mostly long ago) had both fast and slow RAM, accessed directly by the CPU for the fast RAM and through a memory controller for the slow RAM. The Amiga did this. Even many modern PCs can do this. If you have a matched pair of faster RAM modules in a pair of DIMM sockets on one channel, and a slower matched pair of RAM modules in the DIMM sockets of a separate memory channel, then many CPUs will be able to run each channel at it's best speed. There is no reason you can't have a high speed memory controller with some channels directed to on SoC chiplet RAM (HBM or HBM like), while _ALSO_ having some memory channels reserved for slower slotted RAM (either in SODIMM or the newly developed CAMM socket). There is literally no reason a computer manufacterer can't do this, particularly in lower factory memory configurations, where less high speed Factory installed chiplet SoC RAM is installed. You say "sure", like it's something unbelievable... I work on laptops every weekday. More have slotted RAM than don't, and some already solder some ram on board, and have a secondary slot for expansion. No reason you cant have some higher speed RAM on the SoC, as configured from thenfactory, and use other memory channels for slower socketed RAM. I'd LOVE to have sockets in my Mac Studio, so I could add to the already present 32GB of high speed RAM... But YES, Apple is being stingy, because they are profiting on people buying the RAM they _expect to use someday_ right now, while it's still expensive, rather than just buying the RAM they know they need to be high speed, and adding slower RAM in the future to aleviate usage for miscellaneous tasks, freeing up the high speed RAM for more intensive tasks.

Just to note it's only on the 4k youtube setting, if I bump it down to 1440p or 1080p, the issue disapears

Hate to burst your bubble, but the CPU design timeline is such that they would have been actively working on this CPU design for *years* prior to review samples being available.

@@bradley3549 be that as it may, a lot of things, like the ability to use the onboard cache like system ram, are minor revisions that can be made in firmware or opcodes, the kind of tweaks that can happen at the end. The extra cache was planned for years. Booting from it was my idea.

@@aarcaneorg You're definitely not the first to think of integrating ram and CPU and then booting from it. That's been a feature of CPUs for a LONG time. Just not x86 CPUs. Sorry.

Mainframe is a bit different in terms of architecture and targets

Mi300 APU

@@IamBananas007 24 cores, but yeah fair point. :D

Well, Phoronix published reviews of the Newest AMD Epycs inluding Bergamo and they literally destroyed even the HBM version Sapphire Rapids chips....so apparently AMD doesn't need HBM

@@tomstech4390 their MI300C has no GPU cores at all and is 96 Zen4 cores with HBM, but it's unsure whether they will release it since there might be not enough demand for it since their V cache already gives them a lot of memory on-die

Won't make much difference.