Thanks for the kind words. I agree that life is a bit short to grasp everything, which is partly why I feel the need to store some of what I've learned over the years in the hope that others might accelerate their learning.

*Summary* *Project: Designing an Analog-to-Digital Converter (ADC) for Chip Submission* * *0:00* Introduction to the project: submitting an open-source ADC design for a tape-out (the process of fabricating a chip). The speaker highlights the affordability made possible by the TinyTapeout initiative. * *1:56* The speaker's ADC design is the result of years of work, inspired by a 2009 conference and collaboration. * *4:08* Explanation of the system they've developed to generate chip layouts programmatically, focusing on creating high-performance ADCs. *The ADC Design* * *7:21* Overview of the ADC, which uses a common SAR design with specialized techniques for efficiency and portability across different chip fabrication processes. * *14:16* Key aspect: the ADC was compiled, meaning its layout was generated from code, a unique approach in this field. *Compiling ADCs* * *14:49* The speaker boasts that their compiled ADC achieves performance comparable to the best ADCs. * *15:08* Explanation of the compilation process: layout is generated from code that captures design knowledge. The initial system used Perl, but it was ported to C++ for speed and with the goal of making it open-source. * *16:50* Key components of the compilation system: netlists (describing connectivity), placement information, and an object description file. * *18:32* The speaker's motivation to port their system to Skywater 130, an open-source process, to enable sharing their work. *How the Design is Encoded* * *18:43* The goal is to put everything needed for layout generation into text files. The system is intentionally simple, without AI. * *19:17* The design process starts with basic rules, defining even the transistor level. * *22:06* Example using a Spice netlist to describe connectivity in an inverter. The compiler uses this information for device placement. * *25:22* Moving to complex cell design, using Spice netlists for placement and JSON for routing instructions. *The Power of Compilation* * *29:33* Demonstration of how the system makes porting to different technologies easy. * *30:58* Starting the process of porting the ADC design to the Skywater 130 process. * *33:22* Challenges: the system is difficult to use, requiring both analog design and coding skills, which are rarely found together. *How the System Works* * *34:34* Overview of the process: start with an idea in Xschem, generate a Spice netlist, define layout and routing, then use tools to create the layout files. * *37:13* Demonstration of the compilation process and GUI for visualization. *Porting to Skywater 130* * *46:44* The compiler enables porting to technologies like Skywater 130, and the designs pass DRC/LVS checks. * *48:03* Explanation of using the TinyTapeout analog template and setting up the design. * *50:45* Manual routing in Magic was required for some parts of the design. * *51:10* Explaining the CIC file (intermediate format) and its structure. * *53:17* Highlighting the challenge in writing the JSON and Spice files for the system. *Project Setup and Simulation* * *55:44* Overview of project organization, using submodules for reusability and scripts to streamline tasks. * *57:20* The compiled schematic, while functional, is not visually appealing. * *59:13* Routing in Magic, demonstrating its speed and DRC features. * *61:41* Explanation of where DRC/LVS commands are found and how to adapt them. * *1:03:56* Demonstrating the ease of working with older design versions using LVS for verification. * *1:04:26* Explanation of the simulation setup, including parasitic extraction and the importance of simulating across different process corners. *Verification, Analysis, and Tape-out Preparation* * *1:06:28* The speaker's verification plan for the ADC. * *1:07:44* Tools and scripts used to manage simulation complexity. * *1:12:33* Analyzing simulation results using Python scripts. * *1:15:35* Process of generating the GDS file for tape-out, and final fixes. *Conclusion* * *1:16:53* Gratitude for the TinyTapeout initiative and the feeling of accomplishment in having the design ready. * *1:17:19* Emphasis on the open-source nature of the project and encouragement for others to explore and learn. Disclaimer: I used gemini advanced 1.0 (2024.03.04) to summarize the video transcript. This method may make mistakes in recognizing words and it can't distinguish between speakers.

thanks!

The CDAC schematic does indeed only contain metal resistors. The capacitors are parasitic capacitors between metal lines, so they only appear once the parasitic netlist is extracted. The metal resistors are used to separate nets and get the LVS correct.

On tinytapeout I believe it's max up to Metal 4 (locali, metal 1 - 4), but I'd check tinytapeout.com/specs/ to be sure.

1) Yes, quite a few dummies 2) I have not tried EM on the SAR. If you can find EM setup for sky130nm I would try CAP32C_CV, anything more complex might be too much for EM

The closest I have is probably kzfaq.info/get/bejne/ndVgZb1exJncY6c.htmlsi=pnmMrV3nhDvUapqo