virtual sequence & virtual sequencer w.r.p.t system Verilog UVM.

Рет қаралды 10,602

2 жыл бұрын

In this video, I have explained the concept of "virtual sequence and virtual sequencer w.r.p.t System-Verilog UVM".
If you are new to this concept, You just need to pay attention to the details, & then you will find this concept as a "piece of cake to understand"...
#vlsi #faq #interviewquestion #uvm #verification #semiconductor #virtualsequence #virtualsequencer #electronicengineer

Пікірлер: 24

@easytunesparks1317 Жыл бұрын

Informative... Thanks for adding the video...

@kirtikansal6946 Жыл бұрын

kudos to the energy that you put in explaining the toughest topic, relating the codes and the diagrams, making the learners more enthusiastic to grasp more.. appreciable efforts.

@MunsifMAhmad Жыл бұрын

Thanks 😊

@mayankyadav2720 Жыл бұрын

Very good explanation sir , keep on covering topics sir. Very helpful for us. Keep the good work up ! ❤️

@MunsifMAhmad Жыл бұрын

Small correction @6:19 .. Virtual sequencer is a component class in the UVM base class hierarchy, hence it's default constructor has 2 arguments.. @8:58 -> difference between object and component classes.

@bestenglishlearning5049 Жыл бұрын

So good in explanation. Good luck Sir.

@j_______patil2920 Жыл бұрын

Tqs for explanation 😃😊

@user-bm4ig4fw1t 4 ай бұрын

great job

@ichus0098 Жыл бұрын

What is the use of `uvm_do_on macro and 'uvm_declare_p_sequencer() in UVM virtual sequence ?

@MunsifMAhmad Жыл бұрын

`uvm_do_on This is the same as `uvm_do except that it also sets the parent sequence to the sequence in which the macro is invoked, and it sets the sequencer to the specified SEQR argument. Reference:- verificationacademy.com/verification-methodology-reference/uvm/docs_1.1a/html/files/macros/uvm_sequence_defines-svh.html#:~:text=%60uvm_do_on,-%60uvm_do_on(SEQ_OR_ITEM%2C&text=This%20is%20the%20same%20as%20%60uvm_do%20except%20that%20it%20also,to%20the%20specified%20SEQR%20argument. This macro is used to declare a variable p_sequencer whose type is specified by SEQUENCER. Reference:- verificationacademy.com/verification-methodology-reference/uvm/docs_1.1a/html/files/macros/uvm_sequence_defines-svh.html#%60uvm_declare_p_sequencer

@shubhampandey7275 Жыл бұрын

But here also, in case of multiple agents with seqr, testcase writter gets dependent on testbench writter to know the number of such agents with seqr... Then how is this clearing their dependency??

@UVLS Жыл бұрын

Instead of knowing the entire hierarchy to the agent sequencer , the testcase developer will just get details of virtual sequencer from the testbench developer . which helps testcase developer to develop complex scenarios .