What You Need to Know When Routing DDR3 Part 1 of 2

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Күн бұрын

There’s a lot of talk about the 3rd generation of Double Data Rate memory known as DDR3. We at Nine Dot Connects have laid out several DDR3 boards in the past three months. There is quite a bit of detail to know about DDR3 design and layout and unfortunately, there is also a lot of misinformation out there. We have waded though and analyzed the literature. We wish to share our findings and understanding with you.
In our two-part series on this topic, we will first cover key concepts necessary for proper signal integrity and general DDR3 design. Topics to be covered this month are:
• Brief history of the DDR concept
• Comparison between the different generations of DDR
• The signaling and timing requirements for DDR3
• Understanding match length versus match delay
• Compensating for typical routing delay
• Using the iCD Stackup Planner to assist in delay matching calculation
In part 2, we will build upon this foundation by demonstrating the practical aspects of DDR3 layout techniques.
Would you like to see other webinar recordings or videos from us? Check out ninedotconnects.com/knowledge or reach out to us at info@ninedotconnects.com or 214-699-7719. Thanks!

Пікірлер: 16

@ehsanbahrani8936 7 күн бұрын

Thank you ❤

@Nichetronix 5 жыл бұрын

Thanks for this. BTW Sean's card has a misspelling on it: "Principle" should be "Principal".

@bloguetronica 3 жыл бұрын

Very good presentation, although I will hardly develop anything involving DDR3. Thanks for sharing!

@NineDotConnects 3 жыл бұрын

Glad it was helpful!

@ibobaba06 3 жыл бұрын

Do we need VTT termination resistors if we design only a single DDR3 chip? Beaglebone Black board did not use termination resistors. However there are several boards used termination resistors with a single DDR3 chip.

@NineDotConnects 3 жыл бұрын

Ultimately, termination resistors are included in designs to minimize reflections. If the circuits in a single chip solution are correctly routed, the need for such terminations is typically not necessary. However, proper routing techniques may make the cost of the PCB more expensive than the terminations. Only the PCB designer can make the call as to which path is the best solution. For PCBs where pitch and real estate are not problematic, then most designs can get away with not having termination resistors. Having termination resistors gives the designer the option of tuning the terminations for added peace of mind to make sure the PCB is usable.

@jfinnie78 3 жыл бұрын

Thanks for the video and the reference on termination packs, which was a subject that came up between me and another engineer during discussion a couple of days ago. At first I thought this made a strong case for packs vs discrete parts. As I was reading this I couldn't help thinking it was trying to sell me expensive BGA resistor packs, and not putting forward a particularly fair or useful case. Why not compare, for instance, to 0402 instead of 0603, where I imagine the parasitics would be further reduced? On what planet is it sensible to compare terminations for high speed circuits to an axial through hole resistor - really, would anyone think to use such a thing for this kind of application?

@NineDotConnects 3 жыл бұрын

You are correct that 0402 would provide less parasitic, and typically that is the way to go. However, when prototyping, they are more challenging to work with. I don’t, nor have I ever seen anyone else recommend using axial resistors in this application. Resistor packs are typically used when real estate is at a premium, and simulations are available to ensure routing to them is done correctly.

@yetadr 3 жыл бұрын

18:40 ; Do I understand correctly, lane to lane match is the allowable length difference between different bytes?

@NineDotConnects 3 жыл бұрын

Lane-to-lane matching is not generally required. Most manufacturers do not have such a requirement. The specification in the video was part of one manufacturer’s application note. You will never go wrong in creating such a match if ever in doubt of the need.

@yetadr 3 жыл бұрын

@@NineDotConnects I also wanted to ask. Am I correct in assuming that the cloc always has to be longer than the DSQ? I have seen this requirement for the DDR Cyclone 5:www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an444.pdf (Table 1-24; Page 70) From your experience, how common is this requirement?

@michaelreagan2232 4 жыл бұрын

I generally like what Nine Dots has to offer but beg to differ about a few things. 1. Most of the Micro to DDR we work with are BGAs with somewhere between .8 to.5 mm pitch. Your fan out is not going to work with .5 mm parts. Save yourself all the unnecessary calculations (outer layer) by using Via in Pad ( which has been around for 30 years). I am positive somewhere else on your design is a regulator that requires a VIP in the center Power PAD. It doesn't matter at that point if you have 1 VIP or 100 once you are committed to VIP. The costs are the same for fabrication. There are too many advantages for me to list why VIP should be used. Second, Why would anyone layout a high speed design on FR4. The Dk numbers you are using are to high for high speed boards. Third, Once you have analyzed the design, involve your fabricator immediately. You can not enter random dielectric and cu thickness numbers into a stack up. Give the fabricator your impedance requirements, let them provide your stack up, otherwise your self taught stack up can not be fabricated....reliably. I realize 40 ohms is the target, however 40 on internal layers may not be obtainable. The dielectrics either have to be to close, or the trace widths have to to wide to route. Some inpedances are not easy to make on a PCB There is the problem with all of these tools. I guarantee the stack up will be non symmetrical on each side of a stripline from the fabricator. So if you entering pretty but balanced numbers ...they are vapor ware. Last I checked Altium could not calculate impedance to (one or the other) positive or negative plane. This has been a bug for years. I know because base lined the Altium calculator to a Polar instruments tool years ago. Besides, there is no tool online that matches exactly the impedance calculations that the fabricators obtain. They are close, but still off. I have not found an online toy tool will calculate non symmetrical stripline. I will still give the thumbs up to your presentation, you guys are good

@NineDotConnects 4 жыл бұрын

In regards to your thoughts, we would like to address them one-by-one: 1. Fanout is a process that encompasses many options. Many of those options are controlled by the pitch for sure. However, via-in-pad is a technique that adds significant cost and fabrication time, especially to prototype runs and therefore is not an option for many companies or people. 2. FR4 is a fine material for small layouts. Many engineers use it without any problems and save money doing so. So long as the impact is understood, then FR4 is not a problem. If the impact is not understood, it doesn’t matter what material you select for you will probably still get into trouble. 3. We at Nine Dot Connects have always been in favor of contacting the fabricator at the beginning of a design for their input on stackup. Each fabricator has their flavor of stackup that works for your impedances and their stock. They will typically have access to great tools to give accurate width and space rules for impedance controlled tracks. 4. There are free tools to deal with non-symmetrical striplines. The one we have used in the past gives very good predictions of behavior. But then again, why not just use the fabricator!

@jfinnie78 3 жыл бұрын

TI's PowerPAD (and many others) do not equal via in pad technology. For BGA via in pad the via should be filled and plated over. For PowerPAD the only real requirement is that the drill hole be small enough to not cause large amounts of solder wicking. TI's recommended via size is 13 mil and smaller for minimal solder wicking in PowerPAD applications.