John ... this is absolutely brilliant. I needed to go through this several times, before I understood how it is that you are not throwing away half the SRAM. But now I get it. Thank you.

I enjoyed watching this video. I used to have an Osborne Executive CP/M computer in 1983.

Very interesting way to get beyond 64k with the z80, very cool!

Once built a system using two 64 kB boards with RAM and a 32 kB EPROM for the startup. The system could swap out the EPROM in the low memory allowing a system using 64 Kb of RAM. CP/M of some early version as well as UCSD Pascal was used. A memory protect was built, making it possible to protect any ram in chunks of 16 bytes I think it was. A real time, multitasking, using priority, preemptive scheduling, time sliced, operating system was built. Those were the days...

Excellent explaination of bank switching

Thanks for this video. I've always wondered how this was done. Perfect explanation.

Another great video, thanks John!

Excellent John! Very instructive! Regards, RJM

John, you wrote to me a while back and I caught up to you the other day about my comments being gone when you went to read them. I think I commented on this video. If I recall, my comment was: Typically, a Z80 address 0x0000 thru 0x0002 is a 'Jump to 16-bit Direct Address' instruction to where the Cold Reset routine starts incase its ROM (program space) is in high or low memory of 64k byte space. Thus in the ZX81 computer (to reduce components), the ROM starts at 0x0000 because it does not copy Flash to RAM for use as its ROM - it runs directly from ROM in its lower bank of memory (only 8K in the ZX81's case) and jumps to the first even address after a copy of the ISR table that is just after that adress 0 Jump instruction. So, to theoretically expand my ZX81 to use 32-bit address space of 64k banks of 64k bytes each: The first 64k (bank 0) looks like the classic ZX81 memory map (the ROM and custom ASIC in the ZX81 expects the screen memory, system variables, keyboard, ASIC registers, ISR vectors, and user RAM to be in a certain places within the Z80 64k space). By using two IO addresses to hold a 16-bit bank number, banks 1 through 65535 can then be selected where RAM can be filled with different copies of program space from Flash/ROM and/or used as data space - the actual memory space not in bank 0 being enabled only if the bank select is non zero. These other banks can even have a copy the 8k ZX81 ROM to each lower 8k of each in these banks, or use bank memory as hadware directly mapped to memory for things like high resolution displays. That should allow me to use it as a standard ZX81, but if I code in a BASIC patch to switch banks, a Flash can then be addressed to copy itself, other Flashes, and the ZX81's ROM to various other banks and then multi-task among them. When going to non-zero banks, I can command the ZX81's ASIC to stop grabbing from memory for the display (called Fast Mode), this can suspend the ZX81 ASIC from being a ZX81 or if I map/copy certain data into the upper banks from bank 0, it could be used as a multi-tasking ZX81 or a multi-tasking generic Z80 system. Does this make sense?

Thank you a lot John for this explanation. This is the solution I need for my own system.

My little brother and I had a scheme to switch the North Star floppy controller (read only) in and out (write to RAM) while still using the high RAM it was sitting on. Later, we had a bit of software that did a multi-function share with two terminals. This worked very well, but there was one carnal rule: “Shalt not share stack!” Was not savable, ID you crashed the system horribly! Normally we have three places we could be: ALS-8 or some other running program, the basic interpreter (later version we could have two basic interpreters going), DOS for a better term. You had to coordinate your need for the disk data. We never got the North Star DOS to share. Note: The North Star floppy controller was a read only device, all data written to the controller was done with memory reads. All this is done on an Altair 8800 and an IMSAI 8080. Seen something like what you are doing in the late 70’s for banking memory, this was for a 16-bit computer system that would run in an IMSAI box (need the power make it work). The most we could get work was about 8 64K bankable memory cards before the poor power supply packed it up.

The bank select scheme you describe is similar to what is used in DRAM microbees except that microbees can have ROM and video memory overlaid over the DRAM in the upper 32K memory space. Bank selection on an IBM PC is known as Expanded memory which comprised 16K banks with any 4 banks being mapped into the memory address map.

Loving this series. It brings back many fond memories (my first computer, IMSAI 8080 was Intel 8080 CPU based). The only potential problem bank-switching the lower 32K would be if you wanted to use interrupts or RST instructions as they are fixed into low memory. Also, speaking of waste, rather than tying A16 of the flash ROM low, maybe add a pull-up and a jumper to allow quick way to have 2 versions of your ROM BIOS.

Very good Job.

because i want to pimp an atari 2600, i will go with a 6502 compatible device, the 65816, which has 24 bits of address bits. this way i don't need a bank switching for 512kB of RAM. however, if i want to have a minimum system, the runs with the 6507 or a 6502, i need that kind of bank switching as well. at some point i want to have a Z80 core inside as well, just for the fun of exploring CP/M stuff. however, i am glad that an affordable static ram like the AS6C4008-55PCN exist. and everything in through hole components. retro computing never was that cool and affordable. thanks for the inspiration!

Gary Kildall would be proud!

This would have been revolutionary in 1982, and in fact the Trs-80 model 4 supported 128k using a similar scheme of switching 32kb banks, but pretty much useless in a 64-bit world.

Is there any reason you couldn't have the low addresses stay static and have the high addresses be the switchable banks? I'm just wondering if that is mostly just a personal preference or slightly simpler logic, or if there is an architectural reason why that would be a bad idea.

I am working on my own design right now, and will use a eZ80 in z80 mode for it. I have been thinking about the paging for days now, and i settled for 4 pages of 16k each. I was thinking about using 8x8k pages, because 8k is plenty for a boot rom. But that would mean using 8 latches instead of 4. Another factor in my considerations was, MSX used 16k pages. And i would really like to be able to make my computer MSX compatible. But the most important was this: I want to have one bank with the OS in it. And i want to be able to use diffrent banks in my programs. So i need more than 2 pages. For example i could have one bank for the OS, one bank with a game, and the game could then switch the remaining 2 banks for loading level data or something like that.

I understand how the bank selection works. However, could an MMU have been used with additional functionality? I have not been able to find an external MMU from DigiKey. Do you know of a compatible part and where it is available?

What about the stack and registers. Are they going to be located n the lower 23k ram space?

Hi By switching the low 32K of RAM, doesn't one risk having problems handling interrupts?

Yes, you can swap banks, but how do you run code in it and write it? The Research Machines 380Z and 480Z had a more sophisticated system in 1980. They had memory PAGES each of which was a complex combination of RAM and ROM. This enabled common memory between pages and system ROM and RAM to be hidden from the main Page 1 user TPA. Networking firmware and buffers were on Page 0 along with startup code and BASIC in ROM and HRG video RAM were located on other Pages. If you just want more memory why don't you use a Z180 (or Z181 or Z182) and get a MMU for free and be able to turn Refresh cycles off to run Z80 code faster?

Wouldn't it be better to have the first 32k of RAM be always available when A15 is low and access the banks with A15 high?

The memory diagram says "512MB SRAM" Lol

I like what you have done but I am concerned that you are limiting the TPA to 32k out of the 64k of memory. I was rolling something around in my head and I was wondering, what if you switched 64k banks. Each bank would be a stand alone system. You might have CP/M 2.2 in Bank 0, CP/M 3.0 in Bank 1, spread sheet in Bank 2, etc. There are some gaps here but ...

Wouldn't this be much easier on an eZ80?

Thanks but way too much repetitive, saying the same thing over and over again in the first half of the video!