Z8S180, ICE40HX CP/M BIOS Port Part 2

Рет қаралды 726

2 ай бұрын

Booting code that was assembled from Z80 source code and loaded into a block RAM and testing the SRAM chip.
Check out the discord: discord.gg/jf73DRZvh5
Github repo for this CPU board: github.com/johnwinans/2067-Z8S180
Github repo with the FPGA board that this plugs into: github.com/johnwinans/2057-ICE40HX4K-TQ144-breakout
Github repo for the Verilog Examples: github.com/johnwinans/Verilog-Examples
Z80 Nouveau Playlist: kzfaq.info/sun/PL3by7evD3F52rUbThUNDYGxNpKFF1HCNT
FPGA board video playlist: kzfaq.info/sun/PL3by7evD3F52On-ws9pcdQuEL-rYbNNFB
You can support this channel on Patreon! www.patreon.com/johnsbasement
Music used in this video (Vibe Tracks, Alternate) was downloaded from the KZfaq Audio Library.
#verilog
#z80

Пікірлер: 6

@DennoWiggle 2 ай бұрын

And another cliff hanger! "Timing analysis failed due to presence of combinatorial loops". That warning bothered quite a few times. I think that means it just can't figure out timing. I read you can use --ignore-loops switch (or --force which is last resort). Before I knew better I ended up making my code synchronous so I didn't get the warnings. Looking forward to the next installment where perhaps we will see CPM booting........... I was in awe watching you code in real time. You are good Mr. Basement.

@JohnsBasement 2 ай бұрын

In this case, it turns out to be a simple mistake... that I haven't seen manifest this particular error before. And thank you. You are too kind!