I really appreciate you in not only explaining what you are trying to do, but also explaining other terms and buttons and features surrounding what you are trying to do to help get a bigger picture of why and how we are this thing in vivado. thanks

Great video, there's nothing else online that is as introductory and easy to understand as this video. In fact San Diego State University is instructing their students to watch this to learn how to work with the minized board with has both PS/PL As well. So thanks.

This was amazing. It's always so rare to have somone who can speak english normally making these videos

About 12:20 in, the S_AXI options did not appear. I had to select GPIO or the OK button would not appear. When I completed the Block Automation, the M_AXI_GP0_ACLK input disappeared. Not to worry though, just open up the Zynq Processing System block and edit the properties to enable the GP0 AXI. Then it worked just fine. I've already seen Part 2, which this is a setup for. This stuff is pure gold! You have to fish through a lot of documents to find what these two videos show. Thank you very much Dom.

Thank you! I keep seeing too many PS examples using software. The sight of that "RTL" block in the bock diagram is a subtle, but beautiful thing. That's where the magic happens.

Brilliant video. Really appreciate it. No other material on youtube explained it so easily. I could apply the same principles to my PYNQ boards.

Thank you very much, This is exactly what I´ve been looking for.

Thank you very much. I have followed both videos exactly as explained and changed the .xdc file of ZedBoard and it's working perfectly.

Wow! Amazing I was looking for this kinda tutorial.. please make it more for us.

Many thank for your useful video. I have been looking a while for a video that has both PL and PS code. I hope we could see more videos like this in the future.

@9:03 you should not use RGB LEDs with 100% driven output, they should be at 50% PWM duty cycle max. Below that section (as seen in video) was the standard LEDs for Arty-Z7 that are safe to drive 100%, thanks for video this answered many questions I had.

Finally, someone is explaining this connection, well done!!! Could you please tell me why the option "add module to block design" is greyed out in my program?

Thank you so much for this video as it really stabilized my shaky basics.

Great work Dom, a nice beginner tutorial

Thank you! Useful videos!

Audio quality was fine.

Thank you for great video and clear explanation 🙏

Do you know how to write out the bitstream from Vivado to the flash, to keep the design after power 🚴‍♂️

Exactly what I'm looking for. You da man!

Hi dom, will you do more tutorials on the zynq fpga?

Hi, Thank you for the video Dom. I wanted to know that what max. Speed of IO-PIN of Micro-Zed Board with 7020? I cannot find this information into the datasheet. Can you please help me out here

Very helpful ,thank u

Great Video, Well explained 10/10

This is an awesome video, thanks

so here AND gate giving one output signal. what to do if i need all four combination on input for operating four different code in PS part?

Thank you for the video, very useful for beginners. Can you upload a video on how to write data into DDR memory using RTL data from PL.

@Dom-bo8wd this walkthrough is really really excellent.

Thanks for the tutorial! Should it also work when i use the latest vitis version? i dont get it managed that it works...

I am working with Zybo Z7-10, not Arty like you, but I managed to find constraint masterfile and other prerequisites... Everything else is pretty much the same. But I get these warnings(after I create HDL wrapper), and I don't know what they mean. Can someone explain? CRITICAL WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values. CRITICAL WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.044 . PS DDR interfaces might fail when entering negative DQS skew values. CRITICAL WARNING: [PSU-3] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.035 . PS DDR interfaces might fail when entering negative DQS skew values. CRITICAL WARNING: [PSU-4] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.100 . PS DDR interfaces might fail when entering negative DQS skew values

Thanks for the nice video and explanation. I have a problem generating bitstream, it says ERROR: [DRC NSTD-1] Unspecified I/O Standard: 3 out of 133 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. I searched some sources but could not fix it. Could you help ?

Good One!

How you can use the RTL instantly at 10:58? There have no such option for me in Vivado 2015.1 or it only available for Vivado 2019 ?

great stuff, good explanation.

could you explain how to greate a board file snd how to defind MIO? Thanks.

great. thx.

In our design, axi i2c ip is continuously generating interrupts as soon as we load pl file. Any suggestions

VHDL is not case sensitive, but I adhere to writing code like it were. I don't know if Viviado or Verilog are case sensitive. If someone would comment on this, I'd be grateful. Thanks!

Please make tutorials on the vivado software for ZC706 board

Thank you, great friendly tutorial. But can't we just run the NOT and the AND on the FPGA ? To avoid doing the C code on SDK?. What is the purpose of the processor in this FPGA? Will it not introduce delays if we gonna make a real time system ? Thank you

great video , thank you verry much 😉😉😉

Best tutorial

I assume the "ZYNQ" thing is the PS, right? But usually isn't there multiple CPUs (maybe corext A53, cortex R5 for example ) in the PS and how does the "ZYNQ" know which one to use to do the "NOT" operation?

Hi, Thank you for the tutorial. Very cool. I have one worry, I could not "Add Module to Block Design". What do you think is the problem? the error message mentioned the port type led0 is not recognized. Only std_logic and std_logic_vector types are allowed for ports.

Many thanks for your great videos. I got 3 errors after Launching the Runs at "Generate bit stream". Btw your launch box is 2 jobs mine is 4 jobs, nevertheless I redid it again like yours and still get errors, I couldn't find a solution, can you help me out here? 1- [DRC UTLZ-1] Resource utilization: BIBUF over-utilized in Top Level Design (This design requires more BIBUF cells than are available in the target device. This design requires 260 of such cell types but only 130 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.) 2- [DRC UTLZ-1] Resource utilization: PS7 over-utilized in Top Level Design (This design requires more PS7 cells than are available in the target device. This design requires 2 of such cell types but only 1 compatible site is available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.) 3- [Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run. Many thanks for your time :-)

Excellent video, could you do tutorials using a Zedboard and Vivado from 0?

This is the same as transferring data from ps to pl?

Hello!! What should we do if there are 2 outputs?

love yr style

Can you wire external 5/0 v digital inputs to the mod pins instead of using their buttons and switches?

sir how to run the python on zinc and how to build own fpga for runinng python

Wow!!! Thanks!

can i get master.xdc??

Sorry I just can’t get over the fact that a NAND gate should be less transistors than an AND gate

Bla bla bli bli bu 😅

PS is ASIC, it is not programmable gate array like PL part

Quite explanatory, thanks for that but please don't say bla bla bla :)

Hii! Great tutorial i wanted some help in my project how can I contact you?