Steven Bell

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@ElsieDixon-o2e Күн бұрын

Harris Jeffrey White Angela Wilson Jeffrey

@FoodieFuture-m9u 3 күн бұрын

Johnson Jennifer Clark Helen Walker Barbara

@navidsadeghpour4970 Ай бұрын

For creating a clock by process, you should have inserted one line of code after wait For 5 ns : signal a : std_logic := '0' process begin a <= not (a) ; wait for 5 ns ; a <= 1; end process ;

@botsnlinux Ай бұрын

The line a <= '1'; doesn't do anything in this example... remember that with a non-blocking assignment the signal doesn't get the new value until time passes. So after "a <= '1'", it goes back to the top of the process block and does "a <= not(a)" with the **old** value of a. If you put a "wait for 5 ns;" statement after "a <= '1'" then it would work, but it's not clear what the advantage of this would be.

@firsteerr 2 ай бұрын

thanks for this as someone returning to electronics for my hobby of 9 bit micros i have not sued one for decades , so this really bought it all back for me

@user-ww2lc1yo9c 2 ай бұрын

So its not possible to add breakpoint into code when using teh GHDL, is this correct?

@vrakitine 2 ай бұрын

When I was earning my master's degree, I heard a lot about finite state machines (FSMs), but it was all theory - like clouds in the sky: there's a lot of water, but you can't drink it. I toiled for three months after graduating until I implemented my first FSM in code in 1981. Now, there is a programming methodology based on this concept - v-agent oriented programming (VAOP) - with many examples of its implementation. It's best to start learning about VAOP with this article on Medium: "Bagels and Muffins of Programming or How Easy It Is to Convert a Bagel into a Black Hole".

@SilentJnation 3 ай бұрын

Beautiful. Got an exam tomorrow, helped a lot. Thank you.

@Iachigan 3 ай бұрын

Superb!

@b213videoz 4 ай бұрын

VHDL process is a lie: it doesn't exist 🤪

@user-bx7vo8jx1e 4 ай бұрын

Will you provide a link to sevenseg.vhd or a KZfaq video where you create it so I can get the last step of the simulation to work? Great video BTW!

@mustafacanbakan594 4 ай бұрын

how do we know that the output stays high when both the clock and A go low at the same time?

@botsnlinux 4 ай бұрын

The short answer is that we don't! A real flip-flop will have a "setup time" and a "hold time" which define the intervals before and after the clock edge where the input signal needs to stay the same. If the input signal changes at the same time as the clock, the output will be undefined.

@ALPAY35 4 ай бұрын

thank you for your time

@b213videoz 5 ай бұрын

Why must I even think about VHDL ? 🤪

@geoffreyrichardson8738 6 ай бұрын

Should have used a laser pointer, or a fixed focus camera

@VendorProduction 6 ай бұрын

Thank you omg

@mustafaaljumayli6615 6 ай бұрын

Dude thank you so much. I have an exam tomorrow, this was lifesaving. I subbed and liked🙏🏽

@bradleykingston551 7 ай бұрын

Don't we have to initialize the states?

@bradleykingston551 7 ай бұрын

I meant not initializing but define them, like how does the program know that an idle state represents a 00

@botsnlinux 7 ай бұрын

Ah, the cool thing about this method is that you don't have to specify the mapping of states to bits; the synthesis tool can do that for you. And because it can try a large number of possibilities very quickly, it can (hopefully) find a state encoding that minimizes the number of gates used, or makes the circuit run fast.

@bradleykingston551 7 ай бұрын

Hi! What if i have 3 states in my diagram? can i still use the two bits representation? 00 01 10 11? I won't have to use one of them tho. help please

@botsnlinux 7 ай бұрын

Sure, there's no requirement that you use all the states! Although you should probably make sure that there's a path out of the unused state, so that if it ends up there by accident (power up, glitch, etc) it has a way to get back to a known good state automatically. For example, you could use 00, 01, and 10 for your three states, and then add logic so that the 11 state always goes to the 00 state on the next cycle.

@tomholroyd7519 7 ай бұрын

Although ... for a proper A => B with 3 values, you need a LUT with *9* entries ... hrm

@tomholroyd7519 7 ай бұрын

3-LUT are cool for directly implementing #RM3 implication. Electronic logic circuits these days are already non-binary, with at least "true", "false", and "don't care" (X). The logical value of "Both true and false" is equivalent to "neither true nor false" so you only need 3 values, really.

@velascogualotunadaniel2020 7 ай бұрын

nice video

@engjds 8 ай бұрын

Been at this language for a while and I still pull my hair out on occasions, but lately its all been coming together since using component imports and generics, I tend to think of designs in terms of counters and glue logic, i.e. state machines, if you try and fall back on VHDL doing the power tasks without thinking in terms of hardware behind it, you will create some monstrously bulky designs, KISS method. When you start, dont make the same mistake as I did, when you search for help, ALWAYS make sure the examples are SYNTHESIZABLE (can be programmed into hardware) or testbench which cannot, learn one first, not both at the same time or you might go mental!

@engjds 7 ай бұрын

@@b1tbanger thankyou for that tip, that is helpful!, I am at a point now where I can create mostly functioning designs, but clueless on test bench, if you know any good books let me know

@Moocow2003 8 ай бұрын

thank you!

@JamesHardaker 10 ай бұрын

lip smacking is very distracting

@MadOokami 9 ай бұрын

Glad I'm not the only one

@rezapapi6544 11 ай бұрын

Thank you for clear explanation. I think there is an issue. in this line ( hourplus <= "0" & hour;), I think you should use OR(|) instead of AND (&).

@botsnlinux 11 ай бұрын

'&' here is concatenation (i.e., joining the bits into a longer vector), not logical AND! We need a 6-bit vector going into the digit-splitter, but hours will only be 5 bits. So we tack on an extra zero to make it match.

@victorwaburi2821 11 ай бұрын

Which VHDL editor can I download for free

@botsnlinux 11 ай бұрын

GHDL is a good open-source simulator for VHDL. You can use whatever editor you'd like! (I happen to prefer Vim, but there are plugins for VSCode and plenty of other editors as well.)

@richstaubin333 Жыл бұрын

What is it about the radiant that makes it not great as you put it?

@CuriousCyclist Жыл бұрын

Thank you for taking the time to make this video. Much appreciated.

@rckeith Жыл бұрын

Thanks just what I needed. Great video

@samus4799 Жыл бұрын

Hi, i have experience with Ladder Logic. Do you think this would give me an advantage in learning VHDL?

@engjds 8 ай бұрын

Nope, not unless you used it to siplify logic like using demorgans, karnaugh maps, state machine etc.

@ryanmckenna2047 Жыл бұрын

By far the clearest and both concise on YT. Thanks!

@JohnJohn-gy2st Жыл бұрын

Hello

@jajajaj666 Жыл бұрын

❤

@amgadelgamal4445 Жыл бұрын

Hi, i think there is a mistake in the S0 KMAP 11:44 . 0110 is a minterm, but you accidentally put it as 0.

@keenobaerry3195 Жыл бұрын

not in your class but going through the paces in CompE, thanks

@mavisagyemang3542 Жыл бұрын

Thank you

@oricardoaragao Жыл бұрын

thanks!

@bunnyppl Жыл бұрын

Thank you for taking time to explain how to think about VHDL!😃

@workwillfreeyou Жыл бұрын

Thank you. Can you get longer length probe wires. I have the same scope that you're using and would like to use it on auto repair but have a hard time with the short lead.

@botsnlinux Жыл бұрын

I've never seen probes with leads longer than about 1m, but you can always extend it with your own wire or a coax cable. This may introduce signal integrity issues, but unless you're looking at stuff in the hundreds of MHz you'll probably be fine.

@RyanThompsonrthomp Жыл бұрын

YES. THANK YOU

@carrizzle9586 Жыл бұрын

Are you a professor? Or are you just doing your best impersonation of a pompous college professor? The constant pondering and sucking air through your teeth after posing a question, took me to a bad place in my college career. And that's no offense to you but just a word of constructive criticism as to how these video's might be perceived.

@botsnlinux Жыл бұрын

Sorry to hear that you had pompous professors. The "pondering" is because my brain is slow to generate words and get them out of my mouth. It's something I've worked on, but I've never talked as fluidly as some folks, and probably never will. These videos were created in real-time for the pandemic version of the course, so I was using the equipment I had on hand and had essentially no time for editing. I'll definitely keep the mouth noises in mind and invest in some better equipment for videos I create in the future -- thanks for bringing that to my attention. (PS - you come across as pretty arrogant yourself.)

@carrizzle9586 Жыл бұрын

@@botsnlinux That was such a delightful response how can I be mad at it. Plus the gut punch/exclamation point at the end about being arrogant was brilliant.😂 I'm still laughing about it. I am never mad at a little constructive criticism so I'll try to take the arrogant undertone out of my messages. But good job on the video, other than the few critiques that I offered.

@upupa1394 Жыл бұрын

¿Must/can the architecture of the small modules be in another file?

@botsnlinux Жыл бұрын

Yes, the sub-modules are usually defined in separate files.

@mortalwomprat Жыл бұрын

Super helpful. Thanks a bunch!!!!

@ushousewatch Жыл бұрын

What do you do to compare floating points correctlu

@stephanbokelmann507 Жыл бұрын

Where does the file sevenseg.vhd come from.... am I missing somethin?

@botsnlinux Жыл бұрын

I'm assuming that it's a VHDL module in a separate file that's already been created -- in my course most students have already built this for their lab project before they start simulating stuff. Any module with a matching entity declaration will work with this example testbench.

@epat4706 Жыл бұрын

I've just started using FPGA's and your video series will be a great help. I don't get the 4 pulldown menus on my version 0.10-rc1

@atauygur8104 Жыл бұрын

Exactly the video that i searched for thank you so much for this video.

@shavilagt1072 Жыл бұрын

hacettepe ee gang

@atauygur8104 Жыл бұрын

@@shavilagt1072 kfkckckfkxkxlx

@ishaizilberman7656 Жыл бұрын

thanks!

@user-lf5sy5mv3l Жыл бұрын

You're a hero!

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