Amazing lecture. Being a new grad, I’ve been learning these tips on the job but I really appreciate the simple explanations and hyperlynx sims to go with them. Looking forward to watching the rest of your videos

This is amazing. Best format for this information

very helpful

yyggggggggggggggggg. Gfgggg4

WHAT IS EYE OPENING?

DON'T MAKE DISGUSTING NOISES WHEN SPEAKING!!!!! TAKE IT EASY!!!!!! NO LIKE FOR THAT!!!!

Hi sir , What is rise time and fall time of DDR4. Is the TdiVW is sum of Set up Time and Hold time ? Then the sum rise time and fall time is TdiPW-TdiVW?

You have earned a new subscriber!

Brief and to the point. Thank you for sharing such an instructive video !

Instructive video on Ground Bounce. Thank you for posting !

Brilliant video. I am in the midst of a design issue and seeing explanations like that helps a lot but in my case, it is not only a matter of PCB (routing constraints, passive values and location). These DDR chips are in interaction with an FPGA and then an ASIC based on this FPGA. There are lot more variables in the equation.

DQ bit order can be swapped as long as they remain the same byte group and also nibble group.

The revision 10 of the article was finished on sep. 9 2008, titled "A treatment of differential signaling and its design requirements", by Lee W. Ritchey. The introduction part of the article is as follows: Introduction Differential signaling has evolved into the signaling protocol of choice for nearly all emerging designs. Over the years I have written articles covering specific questions on the subject and have devoted chapters to it in both Volumes 1 and 2 of my book series, “Right The First Time, A Practical Handbook on High Speed PCB and System Design” as well as articles in our newsletters. Along with all of this, there has been a flood of misinformation as well as accurate information in magazine articles, applications notes and design guides. Some of this misinformation makes PCB layout more complex than it needs to be and some of it actually introduces potential malfunctions. In order to help make the design task a little easier and sort through the misinformation, I decided it would be a good idea to pull all of this information together in a single place so this document is devoted to this topic in the hope that it will make it easier for engineers to get up to speed on this subject. Throughout this document I will use actual test data to determine where the limits are. At the end, there will be a list of design rules that apply to all differential pairs along with a list of rules that should not be used as a starting point for creating a full rule set for a PCB or system. This discussion focuses on differential pairs that are routed over planes as is common in PCBs. Differential pairs that travel on wires, such as UTP, are treated in the afore-mentioned books.

Hi sir, do yo provide signal integrity training what will duration of course and fees

Hi sir, when load impedance 5 mega ohm then how trace and driver impedance will match

Much valuable information. I have one question. When we talk about a true differential signal pair, does it necessarily has to be transformer isolation, or does any of the other galvanic isolation (eg. capacitor isolation) would also suffice?

this is gold

Hi Terry! great video! BTW have you ever made a part 3 of the series? Greetings from italy!

Is it the same as SSO?

DDR4 data voltage (AC) was shown on one slide as +-75mV and +-100mV on the next slide? Was one of them supposed to be DC?

Great vid, you simplify these sorts of things very well

Best explanation i've ever seen

simply awesome explaination

Pure fire 🔥

한글로 설명해주실 선배님??

Terry, I always enjoy your videos. Very thorough and easy to understand. Thank you for sharing.

thank you so much terry fox...

Great video, in-depth and concise. ty

Really great video - thanks. Shame you don't have more. Out of interest what software did you use for the simulations?

Thanks for posting these videos. I'm just a hobbyist trying to learn how to build an FPGA board with DDR3 (800, thankfully not 2133) and these videos are immensely helpful.

Informative thank you sir

Thank you so much!! Your videos teaches alot, it is of great help in our career.. is it ok to inbox you sir for any queries?

Very Interestingly explained "Evil EMI" destroyer Terry FOX

You could have filtered the files in the list by typing *U5* on the search box.

Can we configure CDS and ODT by using simulations or do we need expensive high-frequency equipment to tune it in a real prototype?

I understood nothing, I’m not an electrician but I need help. I have a home recording studio and there’s a lot of emi in my room. What can I do to get rid of it??

I thought DDR4 data group uses "pseudo" open drain.

Thanks, Your DDR4 part1 and part2 has allot of very helpful information. Your micron articles referenced were also very helpful.

A great walk through.

Fanatic sir... Thank you so much

you r alive! I missed thoese videos.

Hi @Tery can you have a small session on the ADC (Data converters) used in a Serdes

Thanks for this great tips!!

Thank you !

great

Hi. Time 7:05. you said capacitance?, it should not be inductance?

This tutorial would go well with Signal Integrity Simplified by Eric Bogatin.

I dont recommend nor used these high speed design in critical military , aero space , applications , super computers don't use less than 80nm design and noisy ddr 4 running at 2 Ghz

It's a mess routing now a days

Here's another great video on the subject kzfaq.info/get/bejne/h61gdNOg0ZPTmmQ.html