We_LSI

We_LSI

Hello VLSI enthusiasts...
Welcome to my We_LSI ! This channel is here to help you learn Verilog, SystemVerilog, and UVM.

You can find verilog and system verilog videos here. Planned to cover complete system verilog concepts and also some of the protocol videos. These videos are mainly for freshers and those who are new to system verilog. I might have missed few points while explaining but please make sure to clear your doubts at that instant only.

"It is what we know already that often prevents us from learning" ^_^
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“You don't need more time, you need more focus”

Examples for Constraint #systemverilog | PART-2 |Constraints Q&A #vlsi #learn #coding #semiconductor

17:12

Examples for Constraint #systemverilog | PART-2 |Constraints Q&A #vlsi #learn #coding #semiconductor

2 ай бұрын

Examples for Constraint #systemverilog | PART-1 |Constraints Q&A #vlsi #learn #coding #semiconductor

18:19

Examples for Constraint #systemverilog | PART-1 |Constraints Q&A #vlsi #learn #coding #semiconductor

2 ай бұрын

Constraints in #systemverilog | PART-8 | rand_mode and constraint_mode in constraints #vlsi #learn

18:55

Constraints in #systemverilog | PART-8 | rand_mode and constraint_mode in constraints #vlsi #learn

3 ай бұрын

Constraints in #systemverilog | PART-7 | Bidirectional and Solve-before constraints #vlsi #learn

18:57

Constraints in #systemverilog | PART-7 | Bidirectional and Solve-before constraints #vlsi #learn

3 ай бұрын

Constraints in #systemverilog | PART-6 | implication operator and if-else construct in constraint

13:10

Constraints in #systemverilog | PART-6 | implication operator and if-else construct in constraint

4 ай бұрын

Randomization and Constraints in #systemverilog | PART-5 | with and soft keyword in constraint #vlsi

13:53

Randomization and Constraints in #systemverilog | PART-5 | with and soft keyword in constraint #vlsi

4 ай бұрын

Randomization and Constraints in #systemverilog | PART-4 | dist keyword in constraint #vlsi

16:05

Randomization and Constraints in #systemverilog | PART-4 | dist keyword in constraint #vlsi

4 ай бұрын

Randomization and Constraints in #systemverilog | PART-3 | inside keyword in constraint #vlsi

4:57

Randomization and Constraints in #systemverilog | PART-3 | inside keyword in constraint #vlsi

4 ай бұрын

Randomization and Constraints in #systemverilog | PART-2 | inside keyword in constraint #vlsi

9:00

Randomization and Constraints in #systemverilog | PART-2 | inside keyword in constraint #vlsi

4 ай бұрын

Randomization in #systemverilog | PART-1 | Introduction to #randomization| #oop #vlsi #verification

12:16

Randomization in #systemverilog | PART-1 | Introduction to #randomization| #oop #vlsi #verification

5 ай бұрын

Scope resolution operator in #systemverilog | Introduction & Examples| #verification #semiconductor

15:52

Scope resolution operator in #systemverilog | Introduction & Examples| #verification #semiconductor

5 ай бұрын

Virtual class in #systemverilog | Introduction & Examples| #verification #verilog #semiconductor

15:37

Virtual class in #systemverilog | Introduction & Examples| #verification #verilog #semiconductor

5 ай бұрын

Virtual keyword in #systemverilog | Introduction & Examples| #verification #verilog #semiconductor

12:12

Virtual keyword in #systemverilog | Introduction & Examples| #verification #verilog #semiconductor

5 ай бұрын

Mailbox in System verilog | Part 2 | Examples| #systemverilog #vlsi

12:21

Mailbox in System verilog | Part 2 | Examples| #systemverilog #vlsi

6 ай бұрын

Mailbox in System verilog | Part 1 | Introduction | #systemverilog #vlsi

10:05

Mailbox in System verilog | Part 1 | Introduction | #systemverilog #vlsi

6 ай бұрын

super keyword in #systemverilog |Introduction & Examples|#vlsi #verification #verilog #semiconductor

12:52

super keyword in #systemverilog |Introduction & Examples|#vlsi #verification #verilog #semiconductor

6 ай бұрын

this keyword in #systemverilog | Introduction & Examples|#vlsi #verification #verilog #semiconductor

8:51

this keyword in #systemverilog | Introduction & Examples|#vlsi #verification #verilog #semiconductor

6 ай бұрын

Inheritance in #systemverilog | PART-2 | Examples for #inheritance | #oop #vlsi #verification #dv

8:34

Inheritance in #systemverilog | PART-2 | Examples for #inheritance | #oop #vlsi #verification #dv

6 ай бұрын

Inheritance in #systemverilog | PART-1 | Introduction to #inheritance | #oop #vlsi #verification

5:34

Inheritance in #systemverilog | PART-1 | Introduction to #inheritance | #oop #vlsi #verification

6 ай бұрын

Static class members in System verilog | PART-1 | Static properties & methods in #systemverilog

7:24

Static class members in System verilog | PART-1 | Static properties & methods in #systemverilog

6 ай бұрын

Classes in System verilog | PART-2 Examples |#classes in #systemverilog | OOPs in system verilog

11:41

Classes in System verilog | PART-2 Examples |#classes in #systemverilog | OOPs in system verilog

6 ай бұрын

Classes in System verilog | PART-1 Introduction |#classes in #systemverilog | OOPs in system verilog

10:24

Classes in System verilog | PART-1 Introduction |#classes in #systemverilog | OOPs in system verilog

6 ай бұрын

Semaphores in System verilog | Part 1 | Introduction | #systemverilog #vlsi

7:20

Semaphores in System verilog | Part 1 | Introduction | #systemverilog #vlsi

7 ай бұрын

$unit and $root in System verilog | Part 2 | Introduction | #systemverilog |

13:41

$unit and $root in System verilog | Part 2 | Introduction | #systemverilog |

7 ай бұрын

$unit and $root in System verilog | Part 1 | Introduction | #systemverilog |

6:50

$unit and $root in System verilog | Part 1 | Introduction | #systemverilog |

7 ай бұрын

Threads/Processes in System verilog | fork join constructs & process control | #systemverilog |

10:16

Threads/Processes in System verilog | fork join constructs & process control | #systemverilog |

7 ай бұрын

Packages in System verilog | Part 2 | Examples for packages | #systemverilog |

11:10

Packages in System verilog | Part 2 | Examples for packages | #systemverilog |

7 ай бұрын

Packages in System verilog | Part 1 | Introduction to packages | #systemverilog |

10:24

Packages in System verilog | Part 1 | Introduction to packages | #systemverilog |

7 ай бұрын

Functions and tasks in System verilog | Part 4 | Tasks | #systemverilog |

5:20

Functions and tasks in System verilog | Part 4 | Tasks | #systemverilog |

7 ай бұрын

Пікірлер

@aatibmd991 3 күн бұрын

You are amazing 👌👌

@susheelapatagar

@susheelapatagar 3 күн бұрын

Thanks😁🥳

@aatibmd991 3 күн бұрын

Wow, amazing 👌👌👌

@susheelapatagar

@susheelapatagar 3 күн бұрын

Thank you.

@naveenchakali280

@naveenchakali280 4 күн бұрын

mam explain how to access the automatic ,,, increment_static.count_b

@susheelapatagar

@susheelapatagar 3 күн бұрын

Generally, we can't access local variables outside their function or task directly. However, if the variable is static, as explained in the video, it can be accessed. For automatic variables, hierarchical references are not allowed. To work around this, you can declare a variable in the module (outside the function/task) and assign the local automatic variable to this module-level variable inside the function/task. This way, when you need to print or use the variable outside the function/task, you can simply use that module variable.

@naveenchakali280

@naveenchakali280 18 сағат бұрын

Thankyou mam

@ec-213narendrareddy5

@ec-213narendrareddy5 5 күн бұрын

Upload the example program for fork join

@susheelapatagar

@susheelapatagar 5 күн бұрын

@@ec-213narendrareddy5 already uploaded(Members only video) kzfaq.info/get/bejne/n7yKrZyUvbSod3U.htmlsi=2SNSC7jySD8ov9RH

@srinivaskokkonda2999

@srinivaskokkonda2999 6 күн бұрын

Can you generate 2 multiplication table

@susheelapatagar

@susheelapatagar 6 күн бұрын

Sure. Here you go: (Change N value to get any table) `define N 2 class packet; rand bit[31:0]a; int b=1; constraint c1{a ==`N * b;} function void post_randomize(); $display("%0d * %0d = %0d",`N,b,a); b++; //incrementing b value endfunction endclass module pattern; packet p; initial begin p=new(); repeat(10)begin p.randomize(); end end endmodule

@mark_RRR12 6 күн бұрын

GOOD EXPLANATION 👏👏👏

@susheelapatagar

@susheelapatagar 6 күн бұрын

@@mark_RRR12 Thank you .♡

@mark_RRR12 6 күн бұрын

Thanks!

@susheelapatagar

@susheelapatagar 6 күн бұрын

@@mark_RRR12 You're welcome✨ and Thankiew :) You are the first subscriber to send Super thanks.🤝

@ShwetaSPujeri 6 күн бұрын

Best explanation with relevant example ❤️👏

@susheelapatagar

@susheelapatagar 6 күн бұрын

@@ShwetaSPujeri Thank you ❣️

@rohitshet2079 6 күн бұрын

After a long time new video

@susheelapatagar

@susheelapatagar 6 күн бұрын

@@rohitshet2079 yeah.🙋

@vishalgowtham896

@vishalgowtham896 7 күн бұрын

I watched all of your system verilog ------very very helpful mam

@susheelapatagar

@susheelapatagar 7 күн бұрын

@@vishalgowtham896 I am happy to hear that :)

@uditgohil7547 7 күн бұрын

What if it is not time consuming? In order to that we can call directly??

@susheelapatagar

@susheelapatagar 7 күн бұрын

@@uditgohil7547No. tasks cannot be enabled inside the function.(But synopsys and questa simulator allows it with warning)

@Srikarthik 11 күн бұрын

Excellent explanation madam

@susheelapatagar

@susheelapatagar 10 күн бұрын

@@Srikarthik Thank you:)

@Srikarthik 10 күн бұрын

Concept helps a lot! Godgifted madam 🙌

@uditgohil7547 12 күн бұрын

It's working for the pre_randomize function as well, why ?

@susheelapatagar

@susheelapatagar 12 күн бұрын

its because of randomization.if not zero, other value would have been printed right, so in this case 0 only printed thats it. It is also tool dependedent. try with aldec/questa it wont work for pre_randomization.(only in synopsys u will get 0.)

@Hari_krishnaa 13 күн бұрын

We can do with non_blocking statements. But It's another way to swap Good 👍

@susheelapatagar

@susheelapatagar 13 күн бұрын

Yes.

@Eshwarigummadidala1995

@Eshwarigummadidala1995 15 күн бұрын

table is wrong which i compare with ur explaing plz check and correct it

@susheelapatagar

@susheelapatagar 15 күн бұрын

Yeah.Thanks for noticing it. Its not possible to modify the uploaded video. So I have pinned my comment regarding this.

@shaikfaheed7353

@shaikfaheed7353 19 күн бұрын

We_Lsi verify

@susheelapatagar

@susheelapatagar 19 күн бұрын

+Chip verify!

@AshokKumar-pm5vw

@AshokKumar-pm5vw 23 күн бұрын

please upload videos for remaining topics of IPC event regions, Assertions and coverages

@susheelapatagar

@susheelapatagar 22 күн бұрын

@@AshokKumar-pm5vw Sure

@dibyendusarkar4967

@dibyendusarkar4967 26 күн бұрын

😭🤣👬pomnbuio

@KiranKumar-tp3ri

@KiranKumar-tp3ri 26 күн бұрын

We can call by using fork join_none

@gireeshgowda6181

@gireeshgowda6181 27 күн бұрын

Very helpful for the interviews

@susheelapatagar

@susheelapatagar 27 күн бұрын

Yeah.

@susheelapatagar

@susheelapatagar 29 күн бұрын

Example for format specifiers: www.edaplayground.com/x/BEc3

@gauravy997 Ай бұрын

Using “always@(*)” , I am getting b = 5

@susheelapatagar

@susheelapatagar Ай бұрын

I guess you have used synopsys VCS, thats why u are getting 5. Use other simulators and you will get x.

@prasannakumarpatil7243

@prasannakumarpatil7243 Ай бұрын

Hi mam,can you make one session on,how to use %0p,%0d..and /t...etc..please

@susheelapatagar

@susheelapatagar Ай бұрын

I will make one shorts video for that. U can watch that in my "interview questions" playlist ps: kzfaq.infoikghcTU3H20?si=-lh1xBhPPnHjEMt7

@rekhanaik8262 Ай бұрын

Thank you 🎉

@susheelapatagar

@susheelapatagar Ай бұрын

🥰Thank you!

@mounicasegu195

@mounicasegu195 Ай бұрын

Nice explanation. Doubt : Is there any way to delete the particular element in specified index in an array bcz delete method is deleting entire array elements?

@susheelapatagar

@susheelapatagar Ай бұрын

No. For dunamic array there is no way.(Thats why we have queue for addition and deletion)But for associative array we can use array.delete(index_num); You can use this if you really want array element to be deleted:(applies for both fixed and dynamic) int array []; int queue[$]; //-----initial block-----// array = new[5]; array = '{5, 10, 15, 20, 25}; queue=array;//assign array to queue queue.delete(3);//call delete method of queue with desired index value. //---------------------------------------// Thank you.

@boodidasadguna1836

@boodidasadguna1836 Ай бұрын

Is there any possibility to call the task in the function and how?

@susheelapatagar

@susheelapatagar Ай бұрын

Please check out my 1st shorts video. link: kzfaq.infovJKIPTXtdw0?si=8-mJl_kAAE1O1xl9

@ganeshkiran6232

@ganeshkiran6232 Ай бұрын

👍👍👏👏

@susheelapatagar

@susheelapatagar Ай бұрын

Thank uhh!

@rekhanaik8262 Ай бұрын

Thank you ❤

@susheelapatagar

@susheelapatagar Ай бұрын

Welcome:)

@susheelapatagar

@susheelapatagar Ай бұрын

Can you do it using arrays or any other methods?

@susheelapatagar

@susheelapatagar Ай бұрын

Can you do it using arrays/bitwise/** operator?

@ganeshkiran6232

@ganeshkiran6232 Ай бұрын

Your short content is awesome.. kindly make more videos

@susheelapatagar

@susheelapatagar Ай бұрын

Sure.Thank you:)

@rekhanaik8262 Ай бұрын

Thank you 🎉 waiting for more videos

@susheelapatagar

@susheelapatagar Ай бұрын

Bro💜👍

@Prasannakumar-jn7qn

@Prasannakumar-jn7qn Ай бұрын

Can you provide the eda playground link? Thanks

@susheelapatagar

@susheelapatagar Ай бұрын

All EDA links will be available in the respective video description.

@akshayakumars2814

@akshayakumars2814 Ай бұрын

Daily post many videos

@susheelapatagar

@susheelapatagar Ай бұрын

👍

@Hari_krishnaa Ай бұрын

Helpful for a quick learn..😊😊

@susheelapatagar

@susheelapatagar Ай бұрын

Yeah.Thanks

@rrmusic9074 Ай бұрын

What is difference between structure and enum?

@susheelapatagar

@susheelapatagar Ай бұрын

Struct: -Can contain multiple data types (e.g., integers, reals, arrays,strings). -Used to group related variables of different types into a single entity. -Members can be individually initialized. -Useful for modeling complex data structures. -Use the dot(.) operator to access individual members of the struct. -The memory allocated for a struct is the sum of the sizes of its individual members. Enum: -Represents a single data type with a set of named values. -Used to define a variable that can take one of a specified set of constant values. -Values are assigned automatically or can be manually assigned. -Useful for defining states, modes, or other sets of constant values. -Use the enum value directly, optionally prefixed with the enum type for clarity (enum_variable::enum_element). -The memory allocated for an enum is typically the size of an integer that can hold the largest value of the enum.(By default, SV uses a 32-bit integer to store enum values.) Watch my Enumaration video.. Part 1: kzfaq.info/get/bejne/psmTZbia29_LfmQ.htmlsi=SVx8fWej0Xj0GqGO part 2: kzfaq.info/get/bejne/lcVdoqelzbuXhqs.htmlsi=Z17oWdtWnyONL0RB

@susheelapatagar

@susheelapatagar Ай бұрын

Correction: 5:11 By default, no keys are created.The new() method returns semaphore handle or null if it is not created. By default, one key is returned by calling get() if no value is specified.

@srini..... Ай бұрын

Hi Can you tell me how to see the string variables on the waveforms

@susheelapatagar

@susheelapatagar Ай бұрын

We can view the ASCII values of the corresponding string type variables in the waveform, but their names are not displayed and I am currently unsure about how to display the names.

@srini..... Ай бұрын

@@susheelapatagar thanks

@boodidasadguna1836

@boodidasadguna1836 Ай бұрын

2. constraint to generate unique numbers between 99 to 100 module tb(); class packet; rand int a; real y; constraint c1{a inside {[990:1000]};} function void post_randomize(); y=a/10.0; $display("\t\t\t uniquw valus is %2f", y); endfunction endclass initial begin packet p1=new(); repeat(20) begin p1.randomize(); end end endmodule

@susheelapatagar

@susheelapatagar Ай бұрын

Correct✌

@boodidasadguna1836

@boodidasadguna1836 Ай бұрын

3. without inside operator generate random values for the range 34-43 class packet; rand logic [7:0] a; constraint range { (a > 34) && (a < 43); } endclass module tb; packet p; initial begin p = new(); $display("value of a (>34 and <43) is:"); repeat(15) begin p.randomize(); $display("a = %0d", p.a); // Display the value of 'a' end end endmodule

@susheelapatagar

@susheelapatagar Ай бұрын

constraint range { (a >= 34) && (a <= 43); } because 'inside' includes 34 and 43 too.

@boodidasadguna1836

@boodidasadguna1836 Ай бұрын

@@susheelapatagar thanks for correction

@pruthvimelagiri3856

@pruthvimelagiri3856 Ай бұрын

Super 🎉

@susheelapatagar

@susheelapatagar Ай бұрын

Thank you!

@boodidasadguna1836

@boodidasadguna1836 Ай бұрын

Very clear explanation. Thank you 🎉

@susheelapatagar

@susheelapatagar Ай бұрын

Welcome!!

@AshokKumar-pm5vw

@AshokKumar-pm5vw Ай бұрын

Please can you send the example link

@susheelapatagar

@susheelapatagar Ай бұрын

You can find all the code links in the video description.

@AshokKumar-pm5vw

@AshokKumar-pm5vw Ай бұрын

Tq mam

@rekhanaik8262 Ай бұрын

Thank you 🎉

@susheelapatagar

@susheelapatagar Ай бұрын

You're welcome:)

@ramyamarrapu4823

@ramyamarrapu4823 Ай бұрын

Need more videos on Coverages

@susheelapatagar

@susheelapatagar Ай бұрын

uploading soon!

@ramyamarrapu4823

@ramyamarrapu4823 Ай бұрын

@@susheelapatagar thank you

@ANILKUMAR-pj7wo

@ANILKUMAR-pj7wo Ай бұрын

How to override constraints without using soft keyword?

@susheelapatagar

@susheelapatagar Ай бұрын

use constraint_mode and turn of that class constraint check it: www.edaplayground.com/x/wuXH

@ANILKUMAR-pj7wo

@ANILKUMAR-pj7wo Ай бұрын

Tq mam

@ANILKUMAR-pj7wo

@ANILKUMAR-pj7wo Ай бұрын

@@susheelapatagar sure mam

@nehagour9707 Ай бұрын

what a wonderful way to explain the concepts.

@susheelapatagar

@susheelapatagar Ай бұрын

Thanks!!

@boodidasadguna1836

@boodidasadguna1836 2 ай бұрын

Clear cut explanation. Thank you 👍😊

@susheelapatagar

@susheelapatagar 2 ай бұрын

You're welcome:)