SR Flip Flop Explained | Truth Table and Characteristic Equation of SR Flip Flop

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Күн бұрын

In this video, the working of the positive and the negative edge-triggered SR Flip-Flop is explained using its truth table and the timing diagram. And the characteristic equation of the SR flip-Flop is also derived at the later part of the video.
The following topics are covered in the video:
0:00 Why Flip-Flop is preferred over a Latch in Sequential Circuits
6:00 Positive Edge Triggered SR Flip-Flop (Symbol, Truth Table, Timing Diagram)
11:33 Negative Edge Triggered SR Flip-Flop (Symbol, Truth Table, Timing Diagram)
13:13 Characteristic Equation and Characteristic Table of SR Flip-Flop
18:12 Pulse Transition Detector for Flip-Flop
For more info, check these other useful videos:
1) Latch and Flip-Flop Explained
• Latch and Flip-Flop Ex...
2) SR Latch and Gated SR Latch
• SR Latch and Gated SR ...
3) Introduction to Sequential Circuits:
• Introduction to Sequen...
4) Digital Electronics (Playlist):
bit.ly/31gBwMa
Link for the Multisim Simulation :
bit.ly/3tGWBuL
SR Flip-Flop:
In this video, first, the importance of Flip-Flop over the latch in the Sequential Circuits is explained using one example.
And then the working of the positive and the negative edge-triggered SR flip-flops are explained using the truth table and the timing diagram.
The characteristic Equation of the SR Flip-Flop:
The characteristic equation of the Flip-Flop shows the output of the flip-flop in terms of the present state and the inputs.
For SR Flip-Flop if Qn is the present state and, S and R are the inputs, then the next state of the Flip-Flop (Q n+1) can be given as
Q n+1 = S + R' Qn
In this video, the characteristic equation of the SR flip-flop is derived, and in the later part of the video, the pulse transition detection circuit for the Flip-Flop is also discussed.
This video will be useful to all the students of science and engineering in understanding the working of the SR Flip-Flop.
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Пікірлер: 32

@ALLABOUTELECTRONICS 2 жыл бұрын

For more info, check these other useful videos: 1) Latch and Flip-Flop Explained kzfaq.info/get/bejne/grqkqLyWuNOuYps.html 2) SR Latch and Gated SR Latch kzfaq.info/get/bejne/rrV-psSDu7-1nXU.html 3) Introduction to Sequential Circuits: kzfaq.info/get/bejne/nLJ-ZLyA0tulomw.html 4) Digital Electronics (Playlist): bit.ly/31gBwMa Link for the Multisim Simulation : bit.ly/3tGWBuL

@mukuljaitu 2 ай бұрын

Very helpful and informative videos. To the point, all things covered, excellent images and video quality. Literally I prepared for my exam in couple of hours from you the whole content of semester. Thanks bro, Sir ❤

@chandanyogesh9475 5 ай бұрын

ECE saviour 🙌🙏 Thnks a lot sir

@mayurshah9131 2 жыл бұрын

ALWAYS GIVING SOME THING SPECIAL, KEEP IT UP

@anupamaajayan5522 Жыл бұрын

You are a life saver 🙌❤️

@praveenkeshari2088 11 ай бұрын

What a explanation... 🎉

@ChangeMaker0_0 4 ай бұрын

great lecture sir thankyou very much

@VaibhavC-co1bi 10 ай бұрын

Man you are amazing

@guru6333 8 ай бұрын

Sir how sr flip flop using nand gate is different from this Nor gate sr flip flop?

@YdvSyAero 2 жыл бұрын

Sir please also upload video on gated D-latch

@ALLABOUTELECTRONICS 2 жыл бұрын

Please check this video: kzfaq.info/get/bejne/e698lZB117_WaHU.html

@YdvSyAero 2 жыл бұрын

@@ALLABOUTELECTRONICS I have seen .Thank you bhaiya . You are awesome

@nayandutta8315 2 жыл бұрын

Sir are you mr. Mohammed shanawaz sir from heritage institute of technology?sir please tell me. I am eagerly waiting for your answer.

@ALLABOUTELECTRONICS 2 жыл бұрын

Please check the about section of the channel. You will get it.

@user-lk6oc4ii8g 3 ай бұрын

Sir i have a doubt, from the positive edge triggered SR flip flop,in the case where S=1 and R=1 why is the output of the AND gate 1 during clock transition period, and why is it becoming 0 just after clock transition, as just after clock transition, clock input would be 1, so 1 in both inputs of AND gate should be 1 na

@rishithreddygummadi4040 Ай бұрын

It is 1 for a short period of time because of delay see 18:38

@suyashagrawal9834 10 ай бұрын

Its the only place where Gated SR latch is not called a Flip flop , all other places on either youtube or coaching classes call this gated latch a flip flop......... I don't know why people refrain from analyzing using timing diagram, I was so disheartened that such a basic thing is covered wrongly in all places..😢

@Anushka-cn5yv 6 ай бұрын

Exactly 💯 ture

@anonymous9217w2 Жыл бұрын

sir please reply why at 8:20 the flip flop get reset to 0 0 if S is 1 and R is 0., and why we measure Q and not Q'. Please reply.

@ALLABOUTELECTRONICS Жыл бұрын

Please check it once again, when S= 1 and R = 0 then flip-flop gets set to 1. Qn+1 is 1. (The fourth row) Regarding your second question, in the flip-flop design we are getting two complementary outputs. Some times Q' is also used in the circuits. For example, when you design a sequential circuits using Flip-flops then sometimes Q' output is connected to the next stage of the circuit (just to save one inverter)

@6blak197 4 ай бұрын

S and R is present state right(that's what my understanding), then you have to copy the values of S and R in present state right, but you are making everything as 0 and 1 how? Just tell me how we are getting the present state values. I know about the first three rows 8:34 in present state, explain about the last 2 rows for present state.

@6blak197 4 ай бұрын

Understood myself sorry pal ✌️💪

@ajiteshkumar5841 2 жыл бұрын

Sir where are the videos of JK , T and D flipflop.

@ALLABOUTELECTRONICS 2 жыл бұрын

It will be covered very soon.

@yusufislamkcr Ай бұрын

2:12 why the output of this xor gate is equal to 0? Maybe previous stage is 0. I didn't undarstate that.

@ALLABOUTELECTRONICS Ай бұрын

Here, just for explaining, the initial state of the XOR gate is assumed as 0.

@user-ed6ho2om7x 4 ай бұрын

when the present state is 0 1 and the input changed to 1 1 now what is the next state of the sr latch or flip flop when enable is 1

@ALLABOUTELECTRONICS 4 ай бұрын

S= 1 and R = 1 input is prohibited in the SR latch/flip-flop. Because when both inputs are 1, then Q and Q' is 0 at the same time at the rising edge. And after the rising edge, depending on the propagation delay, the output (Q and Q') will be either (1,0) or (0,1). I have already explained that from 8:33 onwards. Please watch it once again. You will get it.

@user-ed6ho2om7x 4 ай бұрын

yes sir i got it thank you so much@@ALLABOUTELECTRONICS

@user-ed6ho2om7x 4 ай бұрын

i got it sir thank u so much@@ALLABOUTELECTRONICS