This training is part 2 of 2. Altera® Agilex™ 7 M-Series FPGAs introduce a hardened, but customizable, Network-on-Chip interconnect, or NoC, at the top and bottom I/O periphery of the device. Including the NoC in a design that uses an external memory interface (EMIF) or on-chip high bandwidth memory (HBM2E) reduces FPGA fabric congestion at the I/O and makes it possible to saturate memory bandwidth, even while running FPGA logic at a slower speed, making it much easier to close timing. This second part of the training describes the design flow in the Altera Quartus® Prime software for implementing a NoC design. It also highlights how to get the best performance out of a NoC design through device resource planning and other optimization recommendations.