14:45 hmm, I wouldn't call this "wild", it mostly looks like what I'd expect provided I ignore the frequency axis. An averaging filter is well known to have pretty meh frequency response, with unit gain only at multiples of f_S (the sampling frequency) and nulls at all other multiples of f_S/N for N-sample averaging. The problem here is that with a 100ms sampling period, you'd expect peaks at multiples of 10 Hz which is clearly not where they're at.

This was a fascinating journey into an area that I've not yet explored. Thanks for posting this. Subscribed.

We really need to ramp up ProPico production 🙏

Thanks NNNI!

Great video man. Love your thoughtfull setup and practical use of sim and matlab. Really enjoyed it. Cheers

Thanks for the presenting a very interesting project. If the sampling interval is 120ms it will not provide *any* 50Hz suppression, no matter how many averages are taken, as it will be sampling the 50Hz interference at the same phase angle in every 6th cycle. I'm sure you know this but for the benefit of other viewers the ramp time has no relevance to the 50Hz suppression - as you observed, this ADC does *not* integrate the input signal over a single measurement cycle. That can only be achieved by averaging multiple measurements. For best NMRR the measurement sampling instances need to be phase locked to, and be equally spread over an integer number of cycles of the interfering signal -eg. averaging two measurements at 10ms intervals will provide a notch at 50Hz (and multiples) and significant NMRR. To complicate matters, the sampling point within each ramp is proportional to the input signal at the sampling instance so whilst it will be the same for each measurement of a DC input signal, adding an AC interfering signal means the sampling point in each ramp will vary accordingly. I'll let you do the NMRR analysis from here onwards :)

Cool project! I might try building a crude version for myself because it seems like a good learning opportunity. I really enjoyed how you explained all the steps you went through to get it working. I can't wait to see what you do next!

Fantastic work as usual!

Very nice, this for sure goes to my list of projects to try! I originally noticed this ADC for the 1980s copium since most stuff i have is 1980s soviet crap, but got scared by programming so didn't get far.

Cool! Very good performance overall. Just as a note, didn't see whether you retained it, but the ADuM140x series can itself be rather noisy, and I would suspect that it might introduce timing jitter. Since these devices use transformers to couple the signal across the isolation boundary, they can only transmit signal transitions (not the actual signal state). Basically they send one type of pulse when the signal transitions high, another type when it transitions low, and nothing in between. The output side needs to latch the signal state. The problem with this approach is that if some noise glitch or other event causes the output latch that stores the signal state to inadvertently flip, the output will be wrong until the input changes again. That would of course be very bad. To fix this, the ADuM140x transmits "refresh" pulses even when you're not doing anything with the signal (the datasheet I saw says this is at ~1us period). It does this whenever the input signal goes more than 1us without transitions (is the case with your signals, I believe). But, of course this means that it's generating noise in the ~1MHz region and above all the time. Potentially worse is that I imagine there might be interactions between the refresh pulses and the data edge pulses. Imagine that you're sending a low-to-high transition but the refresh pulse has already started to send the original "low" state. I don't know how the chip would handle this, but I'd worry it might end up delaying your transition until the refresh pulse was done. This would quite possibly introduce timing jitter to the signals. Not sure what the solution here might be... putting an MCU of any sort on the same rails as the circuit without destroying the performance is going to be very, very hard. Traditional optocouplers might be one approach, although they do have pretty bad timing distortion themselves (not sure how sensitive the circuit is to this as I haven't studied it). It might also be possible to allow the MCU and converter to share a ground reference, but split the power rails completely, and then isolate the digital signals by transmitting them through some reasonably large resistors (~1-10k) and re-buffering them in the converter power domain with some logic gates powered by the analog rails, to restore edge slew rate and drive strength, while still interrupting the noise current path from the MCU's GPIOs.

Outstanding!!!

Wonderful 👏👌

The shitty Pico switcher strikes again!

why not use python or r to analyse the INL? Though to be fair, excel is way more intuitive to use

Not good way too fast booh!