Of course, you are right. Thanks for the correction!

The EM field includes magnetic and electric oscillations, if you must call them photons, fine. Electric and magnetic are components of an EM field/wave, but they are not proportional. You can have electric effects without much magnetic effects and the other way around. The proportion of these components depends on geometry, material and other properties of the effector and medium. FETs don't generate MUCH of a magnetic efect, NOT none. Your comment is like the inverse of astronomers measuring magnetic fields in space and concluding that there's no electric current flowing because the magnetic effect is weak. Kilowatt lasers also generate next to no magnetic effects.

@@PaulSpades ? A kilowatt laser would have a kilowatt of magnetic flux (as well as a kilowatt of electric flux) but it would be nearly undetectable outside the photons. A FET generates no magnetic field, except a negligible field when the charge is impressed or removed.

​​​@@PaulSpades That's a good analogy, but regardless, there should be a clear separation between electric, magnetic, and electromagnetic fields depending on context. In the context of FETs, I don't think electromagnetic and electric fields are interchangeable, but these mistakes happen.

@@xlerb1637 All true. A 1kw laser generates 0.00133 tesla when hitting a surface (assuming perfect absorption): a small bit stronger than a fridge magnet. The FET generates EM when switching(which should cause tiny EM ripples). But also caries electric current when conducting, and you can't have electric current without magnetic waves, as small as they are.

I should have a 10% code ;)

​@@HighYield if you'd get a percentage of their sales - instantly made for life 😁

This is rapidly becoming one of the best channels on KZfaq.

We laugh but itd just get scalped ​@HighYield

lol

So is he German? I kinda thought that by the way he pronounced wafer.

The fun part about being a 2nd language speaker is that you can feel absolutely confident in the domain you're used to and speak about it in detail... But then you can't ask someone to pass you the thingamajig at the table because you never used the what-you-may-call-it and it's right next to the thingy you absolutely know but never had encountered the translation before. I can talk about technical stuff in English better than I can in my native language, even 😅

Indeed. Is he German perhaps?

Not to be rude but this comment section gives me brainrot 💀

Yes

@@TechOtaku86 Maybe your brain was already rotting and you just realized now and having a knee-jerk reaction

Always cool to see an expert in the comment section! Anyways, from what I’ve seen, every new transistor innovation just increases the amount of contact space between the channel and gate, but since we’re already surrounding almost every side of the channel, is this it for transistor design or are there other possible avenues to increase efficiency?

Is Panther Lake the successor to Arrow Lake or Lunar Lake?

I don't know whether or not this has been asked (or published) before, but I'm curious on how you guys build the metals of the M-I-S gates scalably. I work with Si fabrication too and I just couldn't imagine how you guys wrap the metal around a suspended channel like that, at a huge scale with good yields! Is ALD that good now?

@@eddiedoesstuff872 This isn't quite the end, but we are beginning to approach what I would consider an "endgame" transistor design under current manufacturing processes. BSPDN and other technologies to optimize other parts of the chip outside of the transistor scale are going to become very important, which is part of why intel is investing heavily in them now. Advanced packaging and power tech are likely going to be as big a part of a truly next-gen node as much as transistor density is. Being first to the market with combined BSPDN and GAAFET also means they have a headstart on an improved version, which is where the rubber really meets the road.

@@vicktran669 Ideally it succeeds both as an 18A product with new cores and Xe3. I sadly can't say more about it than is already out there.

Always.

Hell yes it is

Yerp

Yeah these hardware deep dives are incredible

They'd probably find a way atp

Definitely a future topic!

Awesome, thank you! Really helps getting that feedback :)

You think software/EDA tools will at some point take over when it comes to chip design? Like no more humans needed?

​@@HighYield I don't know to be honest. You already see this in digital design - more and more of the design is shifted to 'programming'-like, with HDL and such. That said, the standard cells are still often done by hand. In analog, it's a mixed bag. You do see companies trying to push this - though in most cases it is from a 'design-portability' perspective - being able to easily migrate a design from 16 to 10 to 7 to 5 nm, or make small variations (more output driver power, higher current capacity of an LDO, etc). But, at least as far as I understand it, you still do use a lot of manually designed. Even if they are just generation scripts, the best trade-offs in those rules are made by thinking and designing 'the old fashioned' way. When it comes to high speed analog, it is similar, though I think as you go higher and higher in frequency, I think you see less and less automation, as there is more 'fingerspitzengefühl' involved in the desing process. The few attempts I've seen to fully automate the design process have been mixed. I imagine AI will eventually get there, but I don't see it happening in the next 10 years. That said, if you asked me 10 years ago if I would be able to have a pretty convincing conversation with a chatbot by openAI about the intrecacies of millimeter-wave design, I would have laughed you out the room but here we are. ---- What I can say is that with these new nodes, the layouts for analog are starting to look more and more like digital design. Where it used to be you really could tell the individual transistors and so on, you now see more and more that people just create a sea of transistors, all next to each other in a huge grid, and then are connected. In the most recent nodes (like 10 and below) you are pretty much forced to do this, as the multiple-patterning required for forming the gates requires huge repetitive patterns. Usually, these designs also use negative layers, called cut masks - you have huge poly or metal lines that are like 5 um long (which is massive compared to anything else in the FEOL in a 10 nm technology), and then you have a pattern of 'cuts' every 200 or 300 nm that defines your standard cell hight. You also don't get to just chose a transistor width or length - you might have one or two lengths, and two or three widths to chose from. Want a wider transistor? Put more in parallel. Want a longer one? Put them in series and pretend it is a longer gate.

It’s not my usual setup, I recorded in my GFs apartment. And I didn’t want to spend the extra time setting it up 🫣

My goal is to focus more on KZfaq in the future, because it’s difficult to produce quality videos alongside a normal job.

Collabs would be great, but MLID is a clown, has he even got anything correct on release?

MLID.. Oh no please

@@How23497 Yep. TechTechPotato and Asianometry are much better youtubers than MLID.

@@How23497 and have you even got any info not from leaker that true on release. that guy got somethings wrong but not sure a clown cause the only one i see here is you. guy got 10% right and 90% wrong are still better than 0% right and wrong. Leaks meant to change even till the last millisecond before the company present/release/launched. youre probably from wccftech and hey, your next rtx5090 can be 1599$ till jensen decided to change to 2000$ before telling the price

He mentioned it in passing but it seemed like there's now the ability to make 3-D chips that use the vertical direction in many layers. Basically a cube instead of a wafer

Last time was in Taiwan, this time I'm in Germany again.

@@HighYield Haha, well that explains the background change and lavalier mic

Arrow Lake 20A is only Desktop 6+8. Everything else is TSMC N3B. And ARL Mobile is CES 25

With masking you can selectively dope the nano-scale channel with acceptor, donor, or both atoms. If you apply enough electric field, you can deplete, accumulate, or invert the channel, increasing/decreasing its conductivity. The same thing happening in a regular FET.

They already do that - at least sort of. Even with etch it is doable. After all we moved to this (couple layers of transistors on top of each other) a long time ago. This is what decoupled "nanometers" from gate size.

They do this with NAND flash memory, but I think the transistor quality is not good enough for high performance logic.

No different companies, but they have historically the same roots -> Philips

@@my0wn0p1n10n Ah okay, thank you. I was looking for ASM's stock symbol, can't seem to find it, the only other ASM is some mining company.

They are not, but way back in the 80s ASM and Philips founded ASML. Tho today they are different companies.

While you could buy a ASM Atomic Layer Deposition tool for your living room, I think it’s more about brand recognition. Now you know them and what they do. Plus, you know they do really cool stuff.

Lunar Lake is all TSMC(3nm and 6nm, I believe). There is no BSPD. Arrow Lake is expected to have Intel 20A process for CPU die though, which is GAA.

18A team here. LNL is on TSMC 3nm, so no BSPDN. Arrow Lake will have both TSMC 3nm and Intel 20A tiles, the latter having BSPDN.

Good guess, makes a lot of sense.

​@@HighYieldI would guess, it's the next Google SOC. Clearly shared heritage and as such probably easiest to adapt to new Samsung processes, but given Google's market position not as much volume as the Samsung Galaxy S devices.

Silicon is used for its semiconductor property and abundance compared to other semiconductors. Not just because it can be etched into easily

@@pettanshrimpnazunasapostle1992 But thats my point, the semiconductor properties were useful when being doped by gallium or germanium to create the transistor. Now, with the transistor no longer being created from the wafer material, whats the point?

Psst, nicht weitersagen.

Brand recognition and so ppl know what they do I guess. Anyways, super cool sponsor because I'm not shilling something to my audience and ASM has some really incredible technology.

@@HighYield Makes sense. Was on less brain power when I wrote that.

Und es klappt auch noch 😄

He's obviously a deer

What flavor dip we talkin?

I think they'll continue to dip for a while, since they are still missing their road maps, and they haven't gotten EUV perfected yet. They also struggle on their nodes and use TSMC for some chips now. They also are losing hard in servers to amd, who continues to increase core counts and density. But who gets to gate all around first wins high performance compute. TSMC is ahead now, but it's definitly a big bet to think Intel will overtake after a decade of fumbling and they haven't been leading since they first released 14nm

They're going to continue to dip, lunar lake and future chips can't even compete with zen 5 and definitely not with zen 5 x3D

Doubt it, Intel produce most parts of their chips on tsmc for a reason. There is no point in adopting a technology while being unable to produce it efficiently.

I like your positive attitude, but Intel has a long hard road. I'm confident they can do it in the long run, but I'm thinking 5-10 years of hard work to get back what they lost.