- Set design-level constraints ​
- Set environmental constraints ​
- Set the wire-load models for net delay calculation ​
- Constrain a clock for slew, latency, and uncertainty ​
- Analyze a timing report for clock latency ​
- Set the generated, gated, and virtual clocks in a design ​
- Set the input and output constraints relative to the clock​
- Set multicycle paths ​
- Identify and set false paths ​
- Disable timing arcs ​
- Apply case analysis ​
- Constrain paths by setting delay limits
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Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s Intelligent System Design strategy helps customers develop differentiated products-from chips to boards to intelligent systems-in mobile, consumer, cloud data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at www.cadence.com.