Timing analysis is a critical step in the FPGA design flow. To assist designers going through this process, the Intel® Quartus® Prime software Timing Analyzer generates many useful timing reports. The Understanding Timing Analysis in FPGAs course is the first step in learning to use the Timing Analyzer as it introduces the many timing parameters and equations used in timing reports to describe FPGA performance. These include register parameters like setup, hold, recovery and removal, and their associated slack calculations. Understanding these parameters and calculations is key to timing closure, the process designers use when design modifications are needed in order to meet timing .