No video
Crosstalk issue in VLSI | Signal Integrity | crosstalk glitch | crosstalk Noise | part-1
Рет қаралды 22,666
Күн бұрынCrosstalk is an important issue in lower technology node and high-speed ASIC design. What is crosstalk, How crosstalk occurs, What is crosstalk noise, what is crosstalk delay and What are the effects of crosstalk, All these points have been discussed in this session.
Started the discussion with Signal Integrity, basic of signal integrity, then discussed the factors which affect the signal integrity and moved the discussion on crosstalk.
Defined the crosstalk, then given the crosstalk mechanism like Inductive crosstalk and Electrostatic crosstalk, explained various types of capacitances between the routing nets, then various situation on which crosstalk can occur.
Moving forward discussed the crosstalk glitch or crosstalk noise, the effect of crosstalk glitch (crosstalk noise) and crosstalk glitch height with reference of noise margin.
If you feel this video is relevant to your domain and useful, please like the video and subscribe to this channel.
Your queries/suggestions are most welcome in the comment section.
----------------------------------------------
VIDEOS IN THIS SERIES
1. Latchup issue:
• Latch-up in CMOS Tech...
2. Latchup prevention techniques
• Latch-up prevention in...
3. Antenna effect:
• Antenna effect in VLSI...
4. Antenna prevention techniques
• Antenna Effect Prevent...
5. Electromigration issue in ASIC
• Electromigration in VL...
6. IR Drop Issue in VLSI
• IR Drop issue in VLSI ...
7. On-Chip variations
• On-Chip Variation in V...
8. Crosstalk effect in VLSI
• Crosstalk issue in VLS...
9. Crosstalk prevention
• Crosstalk issue and p...
------------------------------------------------------------------------------
Connect with us
All on one page: www.teamvlsi.com/p/contact_8....
Blog: www.teamvlsi.com
Facebook Page: / teamvlsi
WhatsApp Group: chat.whatsapp.com/C6etLHR6oAf...
Telegram Group: t.me/teamvlsi (Or search team VLSI on telegram)
Email: teamvlsi2014@gmail.com
#Crosstalk #CrosstalkGlitch #CrosstalkNoise
@baqirhusain5652 4 жыл бұрын
May god reward you for this a thousand times over.....With no classes you are immensely helpful....Thank you sir
@TeamVLSI 4 жыл бұрын
Thanks a lot @Baqir for your nice appreciation. Please keep supporting!!!
@carthyck 2 жыл бұрын
The presentation you have provided is very informative. Thanks for the video.
@TeamVLSI 2 жыл бұрын
Hi Carthikeyan, Glad it was helpful! Keep watching, Keep learning, keep sharing...
@EduQuantix 3 жыл бұрын
Thank you sir, Greetings from Ecuador!
@TeamVLSI 3 жыл бұрын
Most welcome and happy to hear you.
@jyothico8812 3 жыл бұрын
Thank you for the clear step by step explanation.
@TeamVLSI 3 жыл бұрын
Thanks Jyothi.
@durganaga9513 3 жыл бұрын
Thank you sir. Nicely explained
@TeamVLSI 3 жыл бұрын
Welcome Durga!!!
@habibakhatunnesaragi6259 4 жыл бұрын
Well explained....
@TeamVLSI 4 жыл бұрын
Thank you @Habiba
@habibakhatunnesaragi6259 4 жыл бұрын
Great sir thank u....
@TeamVLSI 4 жыл бұрын
Welcome Habiba!
@mozart3575 4 жыл бұрын
Great sir
@TeamVLSI 4 жыл бұрын
Thanks dear!
@mozart3575 4 жыл бұрын
Sir these details are not explained by iit professor's
@mozart3575 4 жыл бұрын
These much details*
@aakashek8526 4 жыл бұрын
Thank you sir. Its awesome crosstalk seems to be very easy
@TeamVLSI 4 жыл бұрын
Most welcome 😊 @Aakash. keep supporting.
@aakashek8526 4 жыл бұрын
Sir can you create a vdo explaing difference of propogated clock generated clock And clock gating and its types
@ArunKumar-wu4px 4 жыл бұрын
Explanation is Superb ..kindly tell me (1)effect of cross talk on same metal layer and different metal layer...which is more significant
@TeamVLSI 4 жыл бұрын
Hi Arun, The spacing in same metal layer is lesser as compare to different metal layer. So cross talk from same layer will be more severe.
@ArunKumar-wu4px 4 жыл бұрын
@@TeamVLSI thank you
@durganaga9513 3 жыл бұрын
Hello sir, is substrate failure also possible with this crosstalk?
@TeamVLSI 3 жыл бұрын
What is Substrate failure?
@akhilalla3247 3 жыл бұрын
how signal integrity effected by antenna affect? Antenna violation will come during fabrication because of that gate oxide will get damaged but how does it impacting my signal. I have watched your Antenna effect videos also. kindly brief me inshort with small example and Thank you for all your videos
@TeamVLSI 3 жыл бұрын
Yes Akhil, In case of there is antenna effect and gate is not completely breakdown.
@TeamVLSI 3 жыл бұрын
Please use time stamp of video to indicate a particular timing of video.
@radhaa6564 2 жыл бұрын
In which case undershoot happens that is victim net is constant 0 or constant 1 please clarify this one
@TeamVLSI 2 жыл бұрын
Hi Radha, The undershoot may occur when the victim net is at constant logic 1 and the aggressor switches from 1 to 0 logic.
@radhaa6564 2 жыл бұрын
@@TeamVLSI what about aggressor net switching, in this video u mentioned 0 to 1 at one time and 1 to 0 at another time please check this in the video
@TeamVLSI 2 жыл бұрын
Hi Radha, I have edited the previous response as it was not correct. Now try to link it with a time stamp @21:20 I have checked the video and I am guessing the reason for your confusion might be case-2 at timestamp @18:19 . But that is also correct I have here talked about the logic level of input of the inverter which is driving the aggressor and victim net. But if you see the logic level at points "A" and "V" then it will help to clear your doubt.
@pavankumarVilasagar 4 жыл бұрын
we see glitch violations between same layers, why not between different layers?
@habibakhatunnesaragi6259 4 жыл бұрын
I suppose due to static logic ....in same metal layer
@TeamVLSI 4 жыл бұрын
Hi @Pavan Thank you very much, for asking such a good question. Actually crosstalk may occur to a victim net from the same metal layer nets as well as inter metal layer nets. But the effect from inter metal layer nets is lesser as compare to same metal layer net because of the distancing between them and routing direction of metal nets. For Example, suppose victim net is in M4. so crosstalk glitch may occur from following nets. 1. Adjacent M4 nets. 2. M3 and M5 (But these are not routed in the same direction as M4 , so area of mutual capacitor will be very less and distance is also large compare to point-1, so mutual capacitance is very less as compare to point-1) 3. M2 and M6 ( These are routed in same direction as M4, But now distance is too large) So most dominating contribution is from same metal layer. Hope I made it clear. Let me know your view on it.
@pavankumarVilasagar 4 жыл бұрын
@@TeamVLSI Thank you for the explanation
Team VLSI
Рет қаралды 12 М.
BalcevMMA_BOXING
Рет қаралды 13 МЛН
Robert Feranec
Рет қаралды 96 М.
Team VLSI
Рет қаралды 16 М.
Jairam Gouda
Рет қаралды 7 М.