It's not that we can just pass our semester exams with ur lectures ..... it's all GATE level content that u r teaching for free👏👏👏 Hat's off to u sir

i learnd more stuff in a 9min video than a 90min lecture

I just clapped with joy at the end. 👏👏 You cannot imagine how fast I understood everything after watching this video...I just enlightened my class knowledge 100 times! The best Electronic course tutorials are here my fellow engineers.

sir its only because of ur videos i cleared my exam..thnx a lot..keep it up

Heroes fight for their people from behind their masks. Neso Academy fights for students from behind an electronic board.

Thank you so much for all the DE videos...they helped me score really good in my finals...

U JUST SAVED MY LIFE THIS SEMESTER

I wish I found your videos sooner. This helped me so much thank you so much for making these videos

Thank you sir, you have exceptional teaching skills!

tommorow is my dld exam.hoping to get good marks because of your videos.

Your lectures are really amazing sir ! I used to hate this subject before I watched ur videos ! Atleast now I am comfortable with it !

Wow! With this knowledge, the possibilities are endless. Imagine, instead of clearing each flip flop's state to zero, you use the same NAND gate but connect it to PST and CLR on each FF in a different way. You could manipulate this to use counters to skip to different values

Your videos are really great. Thank you so much. I cleared my exams with good grade.

Thank You So much Sir...it's just because of you i am able to understand Digital Logic circuits course which is in my present semester.

all your lectures are superb sir. thanks a lot!!

its my exam today and at 3:00 am I am listening to your lecture ......... thnks sir

the lectures are very interesting, THANKYOU very much for the videos

thank you so much sir these videos are so much helpful

Now I'm confident about my interns. Thank you

sir ur lectures are truly worth it gave me great understanding . sir i also want a lecture on how to design a counter which have only the even states.

Thanks Neso i learnt better than 1 hr lecture in college #from #Nepal

you drew the NOT gate symbol in the wrong direction

man you are awsummm.. thanx alott fr videos.. bhot duaa milega humlog ka.. God bless

Thanks sir .Watching from Nepal

I was struggling for 3 hours with a problem. Thank God I watched this video! One minute into the video and ta-da ! Problem solved. :)

Thank you so much sir Your videos helps me alot

bache ki jaan bachali apne bauji ,dhanyawad :))

Thank You Very Much! Your videos have helped me alot.

i don't have any words to thank u

All the lecturers r awesome...I had cleared all my doubts.... specially I liked the flip flops lectures the most.... thanks a lot to neso academy

Sir, you should also mention that we are observing Q as the output...(in the neg-pos edge triggered section in the beginning of the video). And thank you very much for such great videos..appreciate your effort!

Thank you for the important notes in the beginning of the video. That's what the lecturer did not explain which confused everyone LOL

This is very helpful.Thank you sir

Pakka explanation..... awesome.thank you sir

thanks this qs came in exam but with a twist qs was design a ripple decade counter using jk ff without clr and preset signals

Can't appreciate your amazing explanation enough! Just a simple correction- I think (at 7:55) the signs of the NOT gates should be mirrored, for Qc and Qa. Correct me if m wrong here...!

The besttt teacher ever

thank you.........this helped me a lot really!!😉😃

U r great sir....

Excellent logic bhayyaa

thanks, now i am understanding the working of computer

Thanks for your help

Tqs bro u helped me my exam will start 10:00 clock

In my book it says to draw kmap for output states then draw circuit for clear input. Here we are taking just the first invalid state

great jop sir that's amazing

you are great master

Excellent 👍

you are very good sir thanks

Excellent.

good explination man..

Nice explanation

you are a gift from the god to us

sir u r awessome ..

A small Mistake is that when using CLEAR (Qd,Qc,Qb,Qa)=0 then when you are using NAND gate inputs should not be Qd and Qb instead Qd NOT And Qb NOt.

Ty sir for videos !!! This saved my life .

Great

sir u r the best

awesome lectures sir

thanks alot man respect

The first part of the video created a great confusion for me As you had used negative edge triggered FF to make a down counter where Q was the input and Q' was used as clock But as you did not mention here in this video that you considering Q as the output for all....It made me think for a very long while. Hope this comment helps someone else too.

At time 7:11Not gate symbol is reversed and also 7:21 is also reversed. Explanation is very good.

it is very easy method for all ece students

Thank you so much sir. Your videos have be very helpful in my studies. It's just that we cannot find any serial order in your videos which makes it difficult to find which video is next. If you could add a serial order in your videos it would be very helpful.Thank you.

Thank you for best teachings... 1 question : why not to use and gate instead of nand gate?

number 1 content.

MAN YOU ROCK!!!!!

for positive edge triggered FF the race around condition will appear.How could it be used as counter?could you please explain.

Very nice :)

Good morning sir. You have explained that we have to clear the counter after 1001 (9). So upon the arrival of 1010 we clear the counter. My question is when Qd Qc Qb Qa (1010) has arrived, we have that count (which was to be eliminated ), since Qd Qc Qb Qa are our outputs. Is that count momentary bef the FFs are cleared? Or the action of the clear is so fast that the FFs are cleared immediately? Am I missing something? Thank you for the lectures.

Nice 👍

awesome

These videos are really appreciating but in BCD counter we have to use truth table and k - maps while making the mod 10 counters.

nice one !

You have explained that we have to clear the counter after 1001 (9). So upon the arrival of 1010 we clear the counter. My question is when Qd Qc Qb Qa (1010) has arrived, we have that count (which was to be eliminated ), since Qd Qc Qb Qa are our outputs.

sir, if we use +ve edge triggered clock then what about race around condition ?? you taught that to overcome race around condition we use -ve edge triggering .

thank you neso

It is indeed a fabulous lecture ..which content clear ...but only one correction at the en d..for the two input nand gate you must take qc and qa as 1 nand 1 is 0 but in the lecture the two inputs are qd and qb whose nand is 1 and clr would be 1 ..And sorry for poiniting out such a silly mistake for a great lecture . And shouldnt we stop at 1001 and not at 1010 , because 1010 might also be printed , becoz we are print qd,qc , qb, qa? Correct me if I am wrong

if we place positive edge trigger how can it be JK flipflop??

Hi ..how is the clear input have inverter (bubble form) if the zero out of NAND gate its will be logic 1 ?

thank you

I seriously love KZfaq!

Hello, if I have a asynchronous/ripple D flip-flop counter with a count sequence of 10, 9, 8, 7, 6, 5, 4, 3 and repeat but with provition for a logic 0 output on 8 and a logic output on 6, how exactly would I go about with this kind of a question. I understand that I will use the positive egde triggered and Q would be the clock. I would the connect the NAND gate with input 3 to clear to ensure that it will repeat the sequence but what of the provitions and would the sequence start at 15 and go down or would I also need to connect a NAND gate to PRE so it starts at 10. Any help would be much appreciated.

earlier in down counter video, you used negative edge triggered and Q as clock, you have not mentioned that in this lecture?

great!

So for ripple counters, all we need to do is determine the number of states we have in the count sequence and then attach the clocks according to the type of edge trigger? Do we use synchronous counters to implement the circuitry for sequences that skip states like 0, 1, 2, 4, 6?

You really work hard, I'm worried because I clear concept here but what about semester exam we've to write more and how will we write because we don't have content?

What type of counter do we get if flip flops include both negative and positive triggered flip flops

What do you mean by (MN) wheather M*N or simply MN at the time of cascading the counters??

doing a Greta job.keep up

Can you explain any explain in which clear is applied to particular filp flop.. Eg if 4ff are there and in only 2ff clear is used.

when to use nand gate/ and gate for clr input u have giiven bubble at clr means if u remove bubble then u may use and?

Ty✌

Could you please explain how can I make 4 bit up/down BCD ripple counter?

he give 2 clock inputs a and b ,,output of 1st flip flop not given to second as clock,,he gives 2nd input to second flip flop and then ckt is similar,,an logic used that is also different

the best

When to take output in counter with respect to clock pulse in negative edge triggered flip flop?? 1)At the start of clock pulse or 2)At the end of clock pulse

Thanks sir

Please release video about timing diagram & truth table for 3 bit synchronous counter

Could you please tell me how to build a 2 digit counter which can be used to count upto 10

Someone - Hei. What is your campus? My mind - Neso academy