the sound track used at the beginning of this channel's videos is "Be Thankful" by Shannon Kaiser and Kevin MacLeod, if at all some one cares btw.

What is the difference between latch and flip flop? When we use level triggering in the given circuit it will act as a latch, while if we use edge triggering by using a clock pulse to the circuit it will function as a flip flop. The latch is functional only when the signal is enabled, while the flip flop function when there is a transition b/w high to low or low to high in the clock pulse signal.

PLEASE MAKE VIDEOS ON DIGITAL LOGIC FAMILIES (TTL, ECL, CMOS etc) and ADC and DAC conversions. Your lectures are great. Thank you so much for them.

you're too good.... no confusions or flaws unlike the rest of the tutorials.... don't know how to thank you for the your effort you put together in making us comprehend. thanks again :-)

Sir, my request is to add lecture no. in title of the lecture.

Thumbs Up ! U guys are Awesome i have easily understood all the concepts you have been taught, your all videos related to multiplexer etc, are easily understandable. I completely appreciates your work ! No doubts and no questions at all! Great work man , keep going !(y) Thank your Very much

Thanks a lot sir , the lectures are greatly helpful.

I can listen to Neso Academy in my sleep and still learn something. Thank you!

We are using the NAND gate but the eq you write for Q* and for S*is the eq for NOR gate Plz consider it

Thank you so much sir, you are helping a lot by your videos. We all are beneficial with your videos. Keep going sir, we all supports you. Thank you.

Thank you! very clear and impressive!!

What would happen if we were to use NOR gates for the S and R part (gates drawn in yellow) instead of NAND gates?

I thought in an SR latch when the inputs S and R (S* and R* in the case of the circuit you drew) were both 1, that the outputs Q and Qnot were invalid, or unknown. At 3:50 you seem to indicate that when S and R are both 1 the outputs are memory (or in other words they retain the same value). I thought that the case when S and R are both 0 was when the outputs were memory.

Thank you sir, it was worth watching this video..

Wow! U r awesome! Please explain Mechanics and Thermodynamics. Plss!!

the lecture are greatly helpful thanks a lot

Thank you soo much sir , very clear explanation

Thank you for posting !

when we apply clock for flip flops what is the input send to the nand gate while leading edge/falling edge case?

Sir please do videos on logic families...and memories

please make video on ..linear integrated circuit opamp and ...ce cc cb amplifier

Finally I get it, thank you

I prefer a latch made with one input of a OR gate as the latch Set input. The OR gate output is connected to the input of a AND gate. The other input of the AND gate is connected to the output of an inverter. The inverter input is the Reset input of the Latch. The AND gate output is the Latch output and it is connected to the other input of the OR gate. My understanding is that some integrated circuit outputs can not be connected together without measures being taken to prevent damage. I call the latch circuit above a reset master since a high reset input always results in a low output. To avoid confusion figure any part of the circuit that has a high output is in some way connected to that gates or inverters power supply positive connection. To be honest I have not even tested the above circuit but have tested its relay logic equivalent (which is slightly different).

sir, at 4:43 you said that the circuit will only respond to the edge of the clock...but how does the circuit know that is should respond only at the edge because even in this case the output will change during the high period of the clock pulse.

how output will change in positive edge triggering flipflop when it goes from lower to higher state (0 to 1). why output will not change in positive edge triggering flipflop when it remains in higher state(1)? , as the flipflop will be active when its clock input or enable input is in higher state(1).

Great! Thanks again.

well explained sir!

nice explanation

Sir, please upload videos on logic families

i have a doubt ... lets consider edge triggering ....so you said that the curcuit will be active only when the signal makes a transition from low state to high state or vice versa.........so what happens to the circuit during high and low stages

Nand SR latch is in memory mode when set and reset are all 1.This is diffierent from the Nor SR latch.

Sir . I dont know how to thank u. But ....... increadible effort

Q and Q inventory are the memory outputs but u are saying that S* And R* are memory and it is equal to the case 3

Sir, Which reference book you used for this topic .....Tell me because in some books there are different circuit of latch and it's explanation

Appki video mai apne lecture ko dikhya we bahut satisfy hue apki video se. Subscribe bhi kiye hai.

Very nice lecture...

A flip flop is combination of latches in simple terms. There are other types as well but a positive edge triggered flip flop is a negative level latch connected to a positive level latch. This is some weird explanation. He is clearly confused.

बहुत मस्त समझाते हो आप।। धन्यवाद

please add floating point representation videos

why you said that latch works whenever enable is high whereas it is storing memory when enable is low?

Well understanding...

Thank u sooooo much sir .😊

Sir, is in rectangular signal or duty cycle is not 50 percent, if edge triggering is apply then, it is flip-flop or latch?

I am confused about that part where you are explaining the circuit being a Latch. You said that if the control input is enabled and if EN =0 then S* =1 and R* =1, this is what you called memory. However I thought if those inputs are both equal to 1, that this is an invalid state? Also you never defined what R* is equal to, is R* = R-complement + En-complement?

what is the maximum frequency can be given to a flip flop ?

Thank you sir

thank you ....nice present

We say Latch/Flip flops are one bit storage circuits,but in truth table,these circuits have two outputs ,one is complement of other.Thus they can store two bits ,then why we call them one bit storing circuits.Sorry if my basics are wrong,i am new to it :)

which flip flop or latch circuits we use in servers . I am asking because in server we have to use flip flop without delay .

Sir,does clk mean it has only 50% duty cycle?if yes then can flipflop work with a random pulse?

Nice clarification

Why we didn't use three input nand gate to control inputs ...I mean to add clock to ckt...??

best channel on yt.

sir explain the level tri ggering and clock

Thank You

1 MILLION SUBSCRIBERS COMING SOON😁

Sir make a clear video on active low and active high enable input

I am confused on the part where you said that the ckt is only operational when En is high, but then you show that it works when En is 0. Does this mean that the ckt only works when En is 0?

thank you

sir ,do digital ic logic families

please upload digital communication lessons sir

Thank you

Wow.. you made something so easy--so complicated.

In that circuit when you show the difference between latch and flip flop i don't understand why did you used nand gate in front of the clock wire ( when the clock is high or on after the nand gate it should be off and i don't want that right ).

why we are using NAND gate and formulating the expression with OR operation??

Awesome sir

Hi , I think you have done mistake by saying that S*=S(inverse)+En(inverse) , it should be S*=S(inverse)*En(inverse)

WELL DONE

thanks

Thanks. Sir...

Thank you very much sir🥳🥳🥳🥳

You said that whenever enable is high then only ckt will work. but in the above video ckt is working when en=0. I am not getting this.

sir, if clock is what is concerned for determining flip flop or latch why is the circuit for latch operational for en =0 in case of latch as it should have been en=1 as per your words

why we use Enable Pin in this Circuit..??? What's the use of it..?? Suppose...Clock Set's the Certain Frequency for changing the Time of output's...

sir please upload lessons on digital communication and also tutorial problems in digital communications

can u suggest A GOOD BOOK also?

Isn't it the same as a level-triggered flip flop? Why did you say that it will act as a flip flop only under edge triggering?

Superb

sir due to your lectures I pass the B.Tech . Thank You Sir

Thanks

this is not a flop flop, because still it is in level sensing mode,

Question at 3:53 Why is S* = 1 and R* =1 => memory? Shouldn't that create an invalid condition?

what is the difference between Enable and clock?

sir! after explaining Enable : s* = E+(S-bar).. why did you use ( + ) here however the gate is NAND , not OR .. can you explain it to me .. Thank you ..

ohhhh!! is this the difference??? my teacher when I was in colg told that , latch stores a single bit, but FF stores GRP of bits ... sir pls clarify

i dnt get it. why cant the circuit be used as a flipflop while keeping the clock as level triggered?

Very good presentation H/w option B

thnx

Thnks for your guidance. May ALLAH bless you.

Why we are employing two nand gates only in leading , cannot we use other gate like Nor gate?

What is operational and functionsl in given lecture ???

Won't the flip flop as enabled by the clock at 5:05 be functional only when the clock is high? Like I don't get why is it edge-triggered/edge-sensitive in this particular design. Even with a clock, the circuit should remain functional only when the level is high, and not just during transition. Am I right? 🙁🙁🙁🙁

Why when En(enable)=0,S=0,R=0(both inputs=0)? Both inputs can be 1 only when En=1?

Sir, I understood the concept for Nand Gate Flip-flop, BUT how will it work for NOR gate flip-flop because S=1 and R =1 will be invalid for that

but NAND gate outputs a 0 when you enable it. zero is false, and it all works upside down. when you say 'enable' you really disable the positive output, right?

Difference between LATCH & FLIP FLOPS : Latches are level triggered while flip flops are edge triggered.

Please, i don't understand the part about enable being high or low for S star.

sir is there any other difference between flip-flop and latches

Sir as i knew output of a NAND gate S* should be "bar of (S.E)",.. but u r saying it "S bar OR E bar", I'm getting confused there,... plz help,.. Thank u,..

Superb explanation.