Greetings from the Intel 20A BPD team! I was involved with Blue Sky Creek (BSC) in its early stages, but was moved from the team to work on 20A proper before they hit the labs post-silicon. I did my PhD on the development of modeling and optimization methods for chip to chip power delivery, focusing on multi-chip-module designs and finishing in 2020. Feel free to ask me anything about this new technology and I will happily share what I can.

A High Yield upload? Time to fill my brain with all sorts of semiconductor knowledge goodness

It's crazy we've gotten to the point where we can make this stuff at all.

Small clarification regarding the M0, M1, M2, etc labeling. Using the BEOL image from wikipedia at 5:45, you identify and highlight "M0" as the lowest metal layer in the BEOL steps. In your image, M0 would actually be the tungsten metal, which is identified as part of the FEOL processes. M0 is often called a "local interconnect", because it is a metal layer that is laid directly on the Si surface, and is used to connect immediately local transistors together. For example, in an Inverter gate with 1 NMOS and 1 PMOS, where the Drain of each transistor is connected to the same node, an Local Interconnect would be used to connect the Drains, by depositing a M0 layer directly on the Si, contacting the doped areas of the transistors that form the Drain. M0 is made of metals like Tungsten or Ti Nitrite, and not of the typical Copper or Aluminum metals used in higher layers. So M0 is a "special" metal layer used for local interconnects, because it uses different material and has to be deposited and formed in different ways than the other metals, because it's in direct contact with the Silicon. It's also used as the "Contact" metal for higher metal layers that need to reach the Silicon. M0 is the only one that actually makes contact with the Silicon, being deposited directly onto the Sources and Drains of the transistors to form vertical contact structures. Then, when the wafers move to BEOL, the first "typical" metal layer, M1, is made of Copper and it goes down touches the top of the M0 layer. In your BEOL image, you can see that the orange metal layers are labeled Cu1 (Metal 1), Cu2 (M2), up to Cu5 (M5). Each of these layers really comes in a pair of layers, because each Metal layer requires 1 layer for "Vias", which are the vertical structures that make contact between 2 metal layers, and 1 layer for the horizontal metal layers themselves. In the image, "Cu1" actually includes "Via1" (which is the vertical contact between the top of M0 and the bottom of "Copper 1") and "Copper 1" (which is the Metal 1 layer that makes the interconnects between blocks). Both Via1 and Copper1 each require their own photo masks and process steps. Then "Cu2" is actually "Via 2" (the vertical connection between the top of Copper1 and the bottom of Copper2) and "Copper 2", again each requiring their own masks and steps.

damn that was extremely insightful, info that I could never find on any other mainstream analysis channels

I work on Global Foundries' 22FDX process node which is a 22nm FD-SOI process for RFIC layout design and I gotta admit, this would be ridiculously useful in ways I can't even describe for the RFIC or Analog industry. I imagine it'll get significantly more useful the smaller your process node since the resistances get real high real quick when your metal connections have to be incredibly thin and the vias are tiny. If I could put my thick power delivery wires on the back and not have to share the area over a bank of devices with the data wires my life would be a hundred times easier and I could work at twice the speed. This could even allow some sort of automation for the power routing. Everything would become significantly more power efficient and thermally ideal by doing this too. I must admit, I was rather surprised to find there was only one bottom layer metal (M0). In my process node we have M1 and M2, before going to higher layer block routing metals. I guess it makes more sense for a larger process node and for RFIC design

My head actually hurt from trying to comprehend the scale of complexity in designing this. Truly remarkable.

Another fantastic video man👏🏻👏🏻You’re literally one of my top 3 favorite tech channels, great combination of in-depth knowledge and understandable delivery! Please never stop making these quality videos!👍🏻

Wow! Seems amazing, thank you for diving deep into how technology works, there are not many resources dedicated to that

Amazing. I also think having the metal layers for data and power separate could allow for easier "glueing" of smaller dies together to form a bigger chip as you can route the I/O on top without going to the package substrate or even solder bumps. Glue the chips together, then etch the hermetic seal and build yet another bigger metal layer on top of the smaller glued dies to make the I/O path even shorter. Thus you can make a huge die but with smaller yields. That wasn't possible with flip chips, but now one could imagine that being possible.

thanks for the explanation. It was really clear and easy to grasp 👍

Don’t forget that lower thermal resistance is intrinsic to this as well

Great Video! Always a joy to see one of your videos

As an engineer in Kulicke & Soffa 24 years ago this content somehow educates me on the updates of the semicon industry. Thank you.

Very clear explanations, great delivery.

Hey good to see you again buddy!

such a good vid. i've learnt a lot :) thanks mr high yield

another well paced, well-explained semiconductor. Amazing!

must watch channels, especially tech discussions with precise details, epic 🎉

Another banger. Thank you, Mr High Yield

One of the better illustration and explanation. Thank you

Excellent video. I always learn so much from your videos.

Thank you for such an interesting video. A question, do you know if power via will help to scale i/o so analog parts of Chips further down again, as new manufacturing nodes only scale compute further down and analog and sram are lacking there. Is power via helping here in better density again?❤

I'm very happy to see this video. Slight bit of criticism - give yourself time to speak slower sometimes. I'm around 7:56 and it is hard to understand you, it almost feels like you're trying to speak as fast as possible. I don't think it applies to whole video, but it does to some segments, so in the end if the video was 20 seconds longer it wouldn't hurt that much. But your content is top notch - and indeed problem of power delivery and data transfer, wiring etc. is a problem that is constantly evolving. Meaning that even if you find a solution, often people will take it for granted and within couple of years you will have to find other solutions to very similar problems. And yes, half of the evolution of microchips might be smaller nodes, but the other half is how to get them powered and linked. Very underappreciated topic, so I'm glad you're covering it! Good Job! 👍

You didn't comment on heat dissipation, as there will be more layers on the bottom of the trasitons it could become more difficult or even more heat, I hope more videos like this, thanks for the content!

स्पष्ट अवलोकन , प्रज्ञावान विश्लेषण और बहुत सुंदर समीक्षा कुलमिलाकर अर्धचालक यंत्र के विद्युत और संकेत वितरण प्रणाली और तकनीक के विषय पर बहुत सुंदर प्रस्तुती। 👏👏👏👌👌👌

Thanks for the explanations, I really love this kind of videos

People working on these things are heroes. The significance of chip-making cannot be understated.

Finally BSI content that is digestible and can be understood ^^' Thanks!!!

Great explanation. Thanks for doing this.

super technical video, presented in an excellent manor which was dense with actual information... too often, people make videos where they TALK a lot of words, but, dont really SAY anything ! great video

good tutorial very well organized and presented for comprehension. mb

This was fantastic! Thanks!

Awesome Video, thanks!

Woohoo! Yay! Missed ya man! Thanks!

Great article, question on the backside IO routing, obviously the IO's need to connect in some shape or form to the Top Side signal routing, How is this performed, you would have to route from backside through the silicon and out to one of the top side metals? I can't visualize this and at what top side metal layer does the IO connect to? Is there one large via through from back to front?

I don't think it'll be long before that second silicone layer starts playing host to a second layer of transistors.

Man, you rock!🤘Awesome content as always

always so enjoyable to watch! even if i don't understand 90% of what's happening lol.

Such good content!

Very good explanation

do you have a link to the article that the logic/power separation at 7:17 comes from?

The Chipmachine factory ASML have been/are redesigning some parts that I/we make as their supplier. one of the assys was pretty much flipped upside down. but the changes are only expected to hit production in a year or two. Fun to see this kind of tech developments reflect on things that I see happening at work. Because as a supplier of parts you never get the full picture of what they're actually doing.

I would like to know does backside power delivery allows SRAM start to scale with the process node again? It would be interesting

very informative, thank you

Great video thank you.

Awesome, thx! 😍

Excellent work!

Thank you for this video. I now understand a bit of what all the fuss is about, and I think the fuss is fully justified.

I do have to wonder about thermals and whether that will limit the benefits for P cores. The main heat generating component is the transistor layer and this method puts the signal layers in between that layer and the cooling system. People used to polish down their CPUs just to reduce this distance by several nanometres and improve performance so I don't think it would be insignificant

Great video

Appreciate the video, how does this approach translates to clock speeds? If the power network is longer does that mean lower clock speeds? Also if it has so many advantages and even cheaper to manufacture why this hasn't been done before? 17:30 in this frame you can clearly see Mitsui, I had no idea they made semiconductors as well. Are Japanese also at the cutting edge of semiconductor manufacturing?

I consider myself a chip enthusiast (I regularly use and program computing devices). This was very interesting.

This is brilliant; going to change everything

I learned a lot about the old way of manufacturing also!

Since this method works both sides of a die, could it be used to further develop the transistor layer before making the second metal layer?

This channel is just 🤩

Super curious about the primary heat path in this configuration. It seems like it would have to be down into the power layers and ultimately into the substrate and PCB.

Great video :) I was wondering, why don't they create the signal layers first, then the transistors and then the power delivery? That way you would avoid grinding down to the transistors and adding structural support again.

You can never count intel out.

Very interesting. Also crazy engineering.

how is this gonna effect the cooling of the chip? Can the normal cpu coolers still be used?

Great video. I'd love it if you a made a another one about Samsung's backside power delivery mechanism.

I was always impressed that they were able to maintain 10nm for so long

Im curious where you got the image you used for the thumbnail? Was this an AI generated image, or did you find it somewhere? Could you share a higher res version?

Why no video about the qualcomm nuvia chip?

Why is a BSPD not flipped at the end? It gets flipped to build the backside on top of the wafer and should then be flipped again to connect it to the substrate or what am I mistaking? (Timestamp: 11:05)

Double sided circuits on the chip is even more efficient and vias to connect power and signals between both sides. Next is stacked chi been done?

To clearify, this will not affect how these get connected to boards. Correct? It will however mean growing a layer of silicon on the top ofnone of those metal layers. I wonder how that will work out. Im Only used ised to starting with one wafer then building atop .

New favourite channel

Thank you for your fantastic video. I have to think about it for a while because I still don't understand its overall features. When I imagine it as a skyscraper, and its levels are dedicated to different purposes, why do I have to drill a hole into the basement for my power and use the roof of the building for a laser data connection? When I build up a power grid from the first to the tenth floor, then a CMOS layer to the following levels, and then some data layers, I will get the benefit I want, won't I? For the subsequent levels, I would continue this sandwich upside down repeatedly. Then, I have to interconnect those power and data layers. Why should I think about how my power and data will be connected to my socket? I am interested in your answer and want to understand what I am overlooking.

Seems it would help with cooling too, if the transistor layer is closer to the heatsink contact surface

Could you explain how the metal layers interconnectors are built? The ones that go above and below the transistors?

finally a good videoi about powervia!

7:19 WOW!!! 😱

Intel needs to hold for at least 2 more years before their foundries get momentum.

Still don't know how they connect them to pcb front and back both

Thanks for clearing up how the chip is connected to the substrate. I looked for this answer very long, your explanation makes sense 💪💪

Great summary and explanation. In addition to backside power delivery, I think we have already seen another thing that helped with segregation of data/memory and power. That was the use of chiplets or tiles. Instead of having a monolithic piece of Si as one CPU chip that has everything, now they have different chiplets purposely optimized for each function.

Things might get cooler too :)

What about cooling? Having transistor side closer to heatsinks significantly improves heat transfer I would imagine. Considered they are pumping hundreds of Watts into their chips, it sounds like it would actually decrease performance as for e.g. "turbo boost" wouldn't be able to clock as high.

I wonder what about heating and cooling when silicon is in middle layers?

Given the significant benefits of backside power delivery outlined in the video, how might this technology influence the future landscape of consumer electronics, especially in terms of device miniaturization and energy consumption?

I just came here from the video you made about VFET and i was thinking what if Intel mix this new manufacturing process with the lowest node plus newest transistor design and you pop up with all that (with the ribbonFET) Thanks for all the high qualitty content Now i cross my fingers to Intel and AMD uses all this improvements not to make efficient chips but lower the current power draw. A desktop Ryzen 5 or i5 consuming even 30W at high loads would be a great advance

What's huge about this for Intel is that it shows they can produce industry LEADING technologies. The perception is they've fallen off that train, but despite the fiasco that the 14 to 10nm transition was, they kept at and kept at developing new technology. Hoping their foundry ambitions prove successful.

Saying "Design Flaw" is grossly incorrect, as everything in engineering is a compromise, not a flaw.

Next step is stacking transistor layers?

This is going to be **HUGE** for both power efficiency and thermal management

Ma domanda : i prossimi processori Intel desktop di nuova generazione in uscita a fine 2024 , gli Arrow lake desktop che battaglieranno con gli AMD ryzen 9000 , useranno il pp Intel 4 o il piu avanzato Intel 20A ??? Come è possibile che Intel ci sta mettendo tanto per pareggiare il nodo produttivo con TSMC ?

Krasses Video Diggi

In an environment where heat is not an issue yes. I'm just glad you didn't use Disney marketing "AI chip" which doesn't really exist exclusively.

I wonder how this affects heat.

Subbed

Since the first wafer is removed it could be thinner to begin with, saving wafer cost and time to grind it away. Also the final structural wafer wouldn't need to be suitable for transistor production, allowing cheaper materials (failed wafer recycling?) or even something with better thermal transfer.

I never understood why power was on the same side of the wafer... It was basically one of the first things that came to mind way back as a student already. As a student I had to draw PCBs and was taught that the power lines should be as much separated from the rest as possible, for safety and EMI reasons... so I never got why they didn't apply the same rationale in designing these dice.

I think I've seen "Backside Power Delivery". It's ringing a bell, for some reason.

I assume that in MCM chips this advantage of backside power delivery becomes less useful?

Yes so exciting how much tech Intel is to implement this year, I hope they pan out

Backside power delivery is a no-brainer, and was just expecting technology to catch up

The graphics are top notch