This training is part 3 of 3. Designing, organizing, and optimizing a large FPGA design can be difficult and time consuming. Every change made to fix a problem or to help close timing requires the design to be completely recompiled. Not only can this take a long time, but the placement and routing of untouched parts of the design can be affected. In this training, you will learn about incremental block-based compilation, the ability to partition your design and choose which parts should be reused in subsequent compilations. This feature will help you preserve performance and close timing faster. This final part of the training provides some general tips & techniques as well as a methodology for using the feature to close timing.