i have Digital Systems exam in about 1.5 hrs, i somehow forgot how to find the next state, you helped me!

These videos are great! I have been confused with digital logic since last semester and any confusion I previously had has been cleared up! Thanks so much!

We meet once again the night before the final, and once again this guy saves my ass

I was very sad because I hadn't understood this part, but now I am grateful for your explanation. Thanks so much sir.

it was so cool the way you represent things,even though they are confusing but you made them just a piece of cake.perfect!!!!

great video, i was clueless with analysis of sequential circuits, especially state transition diagrams, your video really helped me prepare well for my electronics exam.

You explained this stuff in less than 15 minutes, Thanks!

very thanks sir May Allah give you long life with good health,i just watched your videos and learned every thing that i want.

This is a fantastic presentation.

Thank you so much. Will consider donating.

This diagram has two outputs, A and B, such that A=Qa and B=Qb. Therefore, we need to draw two state diagrams, one for A and one for B. In simple words: copy the state diagram he drew in the end of the video so that you'll have two of these. Now, decide the output of the first diagram by the value of A(A=Qa) and the second by the value of B(B=Qb)

Great explanations!!!!! Thanks

thankuu so much sir for this valuable lecture. It helps in my GATE exam.

Thank you man again

I finally got the concept. thanks

If it gave me 2 inputs x and y, did I need to write them on state table? Or just input x? How should I do to get JA,JB,KA,KB if they contain another input y ? Thank you very much.

As @ROB LAW suggested, there is a contradiction in the equation of K_A=Q_B*x'=J_A*x'. Doesn't this make the circuit erronous? There are situations where Q_B=J_A'. Thanks for the video btw sir.

These videos are great!

nice one bro thanks for increasing my internal marks

thank you sir.....everything is very well explained

Thank you boss,it's very helpful.....you done a great job.....

thanks for all of us for this chanel it very usefully thanks for us

i have a question,when you were drawing state table and diagram.In the circuit at the start there were outputs A and B,but you didnt inculded them in diagram.It is obvious that their values are Qa and Qb,respectively,there is no calculation that needs to be done,all am asking is , was there any particular reason why you din't inculded them?

Excellent Bro ! Excellent

Awesome explanation sir

You are great man...

sen adamsın adam!!! YOU ARE DEEP MAN !!!

Thank you so so much!

What should be done for (1,1) case if JK is replaced with SR flipflop ?

Thank you

Where can I find the reverse of what is shown here? By reverse I mean from state diagram to JK ff implementation

plz give a video ....how to go back that is reverse procedure......from state diagram to sequential ckt

Mistake, Ka = x' Qb not x' Ja, thank you for the amaing lecture series tho

You Are the BEST !!!

Thank you so much sir 🤗

Thanks a lot sir

sir yours is the best channel on youtube but can yu please mention the link for the previous video of present video .!! thank yu :)

Thank You Sir

it's crazy to find flip flops inputs without karnough map . crazy yy !!!! :)

Thank you thank you thank you thank you!

Thank you very much

Thank you so much Sir

OMG THANK U SO MUCH

Thank u so much...✌️

I have a question . Like the previous video by D flip flop we could have used the equations of J-K flip flop from its excitation table like J=Q(n+1) so Qa+=Ja

Thanks sir 😊

I love The Neso Academy becuase of the way how they repeat and repeat and repeat and repeat and repeat until it's stuck on your mind perfectly Really a big thx for this Academy that is a better than 94583256283742539 University

Thanks❤

I think Ka should be equal to x'.Qb ? please correct me if i am wrong.

Thank you

sir, kindly do some example problems for asynchronous sequential design circuits too..

Thanks Sir...

can you please tell the app you are using for annotating

Where do you find your examples from?

Hi, Anyone there could you please help me out..... Why we are using one NOT,AND, OR gate in the input side... I am little bit confused of these circuit.....

Are the input equation and state equations are same ??

if we have an output equation for example y = AB, is it going to change the state table ??

Superrrr sir ,👍👍👍👍👍👌👌👌👌

Sir, could you please post a video regarding asynchronous sequential counters design

Thanks yaaar

thank you habibi

I think in Qb+ there's a mistake, row 5 should be '1' and row 6 should be '0'. Please correct me if I'm wrong.

Will we treat this as Mealy or Moore? Because there is no output equation.

Please check the input equation for KA. It should be KA=X'.QB

Legend

thanks sir ji

Life Saviour

design a logic circuit for a 3 stage register using Jk type flip-flop and And|OR| Not Gate Please how can I this

Tqs sir

why acive low clock is used in jk filpflop???

I have one doubt: in order to find Qa+ why didn't we consider x, Ja and Ka instead of Qa, Ja, Ka

sir can u please make a video on combination of jk and d flop

wont the next state just be values of Qa and Qb from the logic circuit

in design if we proceed without doing state reduction ...is it correct?

In previous video you took D_ff input as next state (Da= Qa+) and here you did it completely different in state table . Can anyone please explain why ?

how do i get input y? please help me

KA= Qb x'

now it's 5 in the morning... don't remember when did i started. still have about 30+ videos left with no more than 2hr starting to think if only i had started studying at least a week earlier i might not have been in this stituation why do i have to do whole sem in a night 😩😩

good

please check 4:47 because its "1" and you said "zero" i dont get it

I need something like this, but backwards...

In the question.. Will the circuit diagram be provided

how to get output " y " ??

is that circuit a Moore circuit?

Anyone knows how the circuit is drawn?

If Qa and Qb are the outputs of gates, then Qa+ and Qb+ ??????

How to fine results of X? Please help me 🙏🏼

How can we remember this jk ff analysis diagram

How u design the circuit....?

check for Kb in 2nd and 3rd

i think topic you are selecting is Synchronous Sequential Logic not Analysis of Clocked Sequential Circuits

11:39 Wow!

If 2 input x and y. Kre ge toh State table kya hoge??

Why he didnt mentioned y?

But what if we have ckt with output (y).. Then wht r we suppose to do..?? Please reply.. I am struggling alot my exam there tomorrow..

in Qa+ the 4th column shouldn't it be 0 ??

This is a Moore circuit isn't it? If so then the state diagram should also be a Moore diagram.

can someone please explain how the Qa+ and Qb+ was gotten

just a thanks is not enough to say

Why is Ka = x' Ja and not x' Qb???