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Hi teacher, Can you add CC(Closed Caption) to your teaching video series ? This is very helpful for people with weak English listening skills. Thanks a lot.

We should be thankful to her rather than criticizing her! She teaches us every single topic briefly but amazingly, i personally love her for the teacher $he is☺️

It's sad that people are getting annoyed over her accent and broken English. I think her english is fine, she is a South Indian that's why her accent is slightly different. For example she is pronouncing circuit as sircute. I understood the topic and I thank her for that.

Ma'am I love this line...."That's nothing but"😅😅😅😅

Digital Loge Design (CS-103) Time Allowed: 2 hours Total Marks: 3 Q No 1: (Marks: 6+4-10) For a 2-to-4-Line decoder with inputs: An A, and outputs: Da Di. De, De 4) Draw the logic diagram of the decoder b) Write the trith table for the decoder Q No 2: (Marks: 24242-6) For a decimal-to-BCD encoder a) What is the function of the encoder? That is, what does this encoder do? b) How many input bits are there? c How many output bits are there? Q No 3: (Marks: 6) Draw the logic diagram of 2-to-1 line multiplexer. Label each stage of the multiplexer. Q No 4: (Marks: 343+4-10 This question is about full adder. a) Write the truth table of a full adder. b) Write an equation for the full adder (there are many equations, you need to write just one of them) c) Draw the logic dingram for a full adder. 2 No 5: (Marks: 4+4-81 For a clocked S-R latch a) Draw the logic diagram b) Write the function table O No 6: (Marks: 10) Write the state table for the state diagram shown in Figure 1. Note that the state table must include present state, next state and output.

Thank you Ma'am. I understand the topic very well. Previously my concept on flip flop was not clear but now after watching your video it is clear now Thank you Ma'am. Good job

Mam you did not c/k down I think forgotten ... THQ for your lectures its so helpful to me...

here in (iii) case, suppose if we get (Qn+1)' = 1 then it is invalid state so, we must required to check both normal and complement of present state. is am i right mam??

very clear explanation!good work!

very clearly explained. thank you madam.

Thank u mam for ur tutorial I am reguraly following ur classes it's very useful nd easier to understand mam

Good job mam . Thanks !!

Mam u r multi talented u r know more than 2 subjects and u r teaching is simply understand by me tq u so much mam 😊 ☺ 💖 ❤

Very well explained..Ty so much😊

What are the drawbacks of clocked RS flip flop? Explain the operation of JK flip flop along with its circuit diagram and characteristic table.

thank you mam best for ever teacher omg teaching professional much talent mam keep continue mam

Thanks ma'am for such a nice explanation.

Thank you ma'ma it's so useful keep doing more videos

Thank you much mam. Ur videos Are really helpful for my sem exams.

pls don't mind the criticising words mam.your teaching is simply amazing 😄.

I have revised my all syllabus with ur help mam.. Can u help us on subject Numerical Methods and statistical techniques also?

Thank you for this, it's well explained.

thank you madam i understand very well

Thanks for the easy explanation.

mam you haven't considered clock value zero...but i know what happens in case of 0 . thanks to you for the concept..... keep making videos

yesssss....finally got it....thanks mam

Your lecture are very good easy to understand thanks 🙏

you are amazing your videos are very explanatory

Wow mam amazing thank you so much for clear my doubts 😇

Nice explanation on sr flip clop

Mam Qn is the output of the circuit just before t=nT?

Super mam.... Your explanation is Nice

Thanking you so much mam,,,I will clarify dougts

isthistheequivalentoftalkingwithoutusingspacingbutorally?

Useful video 👍🏻

love you mam, love the way you teaching 🙂

Ur classes r amazing ma'am...🥰🥰🥰

Ma'm its so helpfull thnx for the info

Excellent 👌

Thank u mam for your lecture

Thank you!

Nice explanation

Very good presentation

Good Explanation

Mam could you please explain the D Latch and JK Latch with waveforms

Well explained

Amazing video

good explanation now i am understand sr flip flop

well explained

I have two questions about circuit related ....can you solute for me?

Madam sr,clocked sr flipflop same or different

Thank you so much Ma'am !

Tq mam i got 14 marks from ur video tq so much 🤗

Excellent explanatiion

Thankyou so much ma'am it helps more ❤️❤️❤️🤓🤓

super sis.......

How can we have acess to this lady complete class..

Good presentation

what is the ic number for sr fliop -flop and latch circuit ic number

Good explanation mam

Thank you ma'am

Ma'am, what will be the truth table for SR Flip Flop when clock = 0 or low?

Very sweet lecture

Nice teaching

Thank you a lot mam but how to improve invalid condition Please explain it mam

What if clk = 0? U said u will discuss.

iski playlist khaa yaar ?

Man Aap meerut m classes krto ky

Thank you

What about timing diagram

where is the timing diagram?

Tomorrow i have exam ur vidoes helping me alot tnaxx madam 💜

Thank you so much

Thanks mam ,very helpful ☺️

Mam your teaching is good, but we not connected with clock ,when we connect the clock it is called clocked SR flip flop.

Ultra legend pro max plus listening to lecture in 1.75 playback speed

thank you

Wowza ❤️

thanks a lot

Mam could u plz explain timing diagram

Thank you so much mam.

Why Qn x andukku pettuma

thanks Mam

Thank you mam🙏

Thank u so much mam

Gd explanation madam

Thanks

Where is timing diagrams

Thank you Maãm. I understand your lectures. From Nigeria

Your lectures helped me a lot to understand flipflops as I missed these lectures in my college

thank you ma'am

Somehow you just taught me logic circuits in broken English. Outstanding instructor.

Why didn't u check second condition for S=o,R=0?

Nice😘

Thank u very much maam

I learnt mam

Thank you maam

Indian KZfaq Buddy Supremacy.

Tq u so much mam