PCIe on Xilinx FPGAs

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PCIe on Xilinx FPGAs

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FPGA Zealot

Күн бұрын

Пікірлер: 49

@sureshdotworks 3 ай бұрын

Thanks a lot for this stream ! I learned a lot of techniques which I never knew before !

@TahaAlars Ай бұрын

Just best stream ever. Big thank you for your time

@damny0utoobe 4 ай бұрын

Good talk on pcie on xilinx/amd

@MrGbps Жыл бұрын

Great video, thanks for making it! On the topic of your BAR resize needing a reboot: You are right that you can’t dynamically reallocate BARs on your devices after device reset without pcie hotplug support with your firmware, OS kernel, and device all working in tandem with the spec. It will especially require help from your mobo firmware, and they are not all made equally. However, the trend is moving that way now that Thundebolt 3 essentially does external PCIe hotswap over the thunderbolt cable. We will see a lot more support in the coming years, and I am curious to know the extent that the Xilinx pcie core supports it as well- my feeling is not.

@fatihcay3387 2 жыл бұрын

You did good work .Thanks a lot!

@dannyprats824 3 жыл бұрын

Hi.. this is a great FPGA channel! so.. my questions: 1) can an Acorn CLE 215+ be flashed through PCIe without JTAG cable? 2) is it mandatory to use a JTAG cable to flash/program? 3) Is there a guide to flashing via PCIe? 4) Can I design in tools like Vivado and then flash / program via PCIe?

@FPGAZealot 3 жыл бұрын

You need to have a FPGA design with both PCIe and the flash on the FPGA already then you program the flash over PCIe. But your first program will probably have to be over JTAG.

@FPGAZealot 3 жыл бұрын

My other videos show my method for programming the flash, but since it's a FPGA you can do whatever you want.

@bertyguilbo8536 Жыл бұрын

Great stuff

@0tsengs 3 жыл бұрын

Hello! I have one quite general question. I have been considering purchase a special FPGA board such like the Xilinx BCU 1525 FPGA and sqrl accorn (as mentioned in your video). But I am always not sure whether such kinds of boards can be programmable by Vivado as like normal FPGA board or not? Although it seems be possible from your video. I really appreciate if you can give me some suggestion.

@Mikey-gs1dx 3 жыл бұрын

If I'm not mistaken, the free version of the Vivado will program the Artix 7 on the Acorn through JTAG but I believe you need the license version of Vivado for the BCU 1525 since it uses the Virtex Ultrascale+

@FPGAZealot 3 жыл бұрын

The Acorn requires you to make a cable to connect the JTAG to a Digilent JTAG USB device. You can follow this guide: github.com/enjoy-digital/litex/wiki/Use-LiteX-on-the-Acorn-CLE-215

@FPGAZealot 3 жыл бұрын

The BCU 1525 has a JTAG USB port, but does require a licensed Vivado version to compile bitfiles like @Mikey said.

@cankocak6505 3 жыл бұрын

Thank you so much for this tutorial, it is very helpful. Is it possible for you to create a video to show how to implement "7 Series FPGAs Integrated Block for PCI Express" on Acorn Sqrl (Nitefury) from scratch? I mean like from empty block design to a minimal working PCIe project on Vivado. I will be grateful.

@FPGAZealot 3 жыл бұрын

A lot of my videos talk about different aspects of this. Is there a specific part of it you have questions about? I would suggest the official nitefury example, liteX acorn implementation, or my recent work. github.com/byuccl/fiate

@PalestinianKnight 2 жыл бұрын

Great Video!

@tomo4294 2 жыл бұрын

Doesn't Xilinx provide a basic driver skeleton?

@FPGAZealot 2 жыл бұрын

Yes, you get Windows or Linux src code.

@MilanNedic94 14 күн бұрын

Do you guys know some good github repo of fixed XDMA driver for Linux? I managed to flash Nitefury with Sample-Projects' out.mcs (I assume their bitstream is good) and I managed to install xdma on Ubuntu 20.04 LTS, the best I could do is to read the temperature and the voltage on the chip but no luck with data transfers due to Unknown error 512 - I am desperately looking for solution. I failed to get anything working through Thunderbolt dongle so I installed Ubuntu on external SSD and replaced my laptop's internal SSD with Nitefury, "Processing accelerators: Xilinx Corporation Device 903f" instantly appeared. Is there some additional setting maybe on host side to be set? Any hint from the comunity is very welcome!

@tigheklory 2 жыл бұрын

This is cool and all, could these PCIe FPGAs be used to run Mister cores that run on the DE10 Nano? It would be awesome to run those cores on my PC.

@film2240 8 ай бұрын

I wonder how I can use an FPGA to speed up tasks like video encoding or other tasks that take a long time on the CPU and sometimes even GPU? As I wish FPGAs were much easier to buy, setup and use with apps I have on my PC. Is there a way this can be achieved or is the technology not there yet? I'm new to the FPGA scene.

@FPGAZealot 8 ай бұрын

The LiteFury 2 is the most affordable option, but the complete lack of HDL, driver, and API make it a hobby project at best. I plan to add some examples later in 2024.

@khaled_ismail Жыл бұрын

44:22 Would it be needed to adjust resistor termination in FPGA transceivers as well as the Server Riser card's re-driver and re-timer? Usage of riser cards can cause the link to not train, due to not detected Tx receivers on some lanes

@Dr.Bigglesworth 5 ай бұрын

Did you ever figure out how to get RWEverything to access the memory addressed by your BAR?

@FPGAZealot 5 ай бұрын

Depends on the address space of the motherboard PCIe enumeration

@Dr.Bigglesworth 5 ай бұрын

@@FPGAZealot Did you get it working for your application? If you're able to get a configured BAR (which you can obviously check with RWE, or for that matter, even configure it with RWE), RWE should be able to access that address region the BAR points to I would think? I understand if the BAR is in 32 bit address space, on a 64 bit OS, that has to be mapped somewhere in the 64 bit address space. In my case, I just used 64 bit BARs, and I would think it would map it into real address space as far as RWE would think... I guess I'm assuming RWE memory read/write it to physical address in 64 bit space on a 64 bit OS.

@Dr.Bigglesworth 4 ай бұрын

I used WinDriver (Jungo) evaluation to make a .inf file for my board, used Device Manager to associate it with my board, and using Device Manager, did a scan for new hardware, and my board board got enumerated. Then I was able to read/write all the memory/GPIO registers behind the BARs. So, the answer is, RWE can access the memory behind my BARs.

@qingyangyi4773 3 жыл бұрын

Hello, thank you for the detailed tutorial. I am working with xilinx xcku1500, windows10. I'd like to use XDMA to transfer data from host to DRAM of FPGA. I am just starting with XDMA IP example design. However, after I run synthesis and implementation, and load bitstream to FPGA, I can not find 'Xilinx Drivers' on Device Manager, as this video shows. Of course I have installed XDMA driver. I am wondering the reasons. Could you help me with some advice?

@qingyangyi4773 3 жыл бұрын

I checked the outputs of XDMA IP -- axi_aclk, axi_aresetn and user_lnk_up -- by linking them with leds. I found that user_lnk_up is LOW which indicates that physical link fails. It is strange because xcku1500 is powered through PCIE.

@jameslu1488 3 жыл бұрын

Hello, Good see you. I have one xilinx VCU1525 Board, I'm looking for Windows 10 PCIe driver,I saw your video. Is it the BCU1525 same VCU1525? Can you please help me the VCU1525 PCIe windows 10 driver? Thank you so much!

@FPGAZealot 3 жыл бұрын

The Xilinx XDMA driver software works just fine. I have it working on Linux and Windows. Check out this link: www.xilinx.com/support/answers/65444.html

@jameslu1488 3 жыл бұрын

@@FPGAZealot Thank you for helping. May I add your mail and chat software. Can you support the vcu1525 bitstream please?

@FPGAZealot 3 жыл бұрын

@@jameslu1488 Feel free to use this email: fpga.zealot@gmail.com

@trendmakerzz7453 Жыл бұрын

Hi if possible any driver available to communicate pcie gen 2 x4 bat address read /write via python in windows?

@FPGAZealot Жыл бұрын

Windows is a difficult platform to develop PCIe for. There is not an easy way to interact with memory.

@trendmakerzz7453 Жыл бұрын

@@FPGAZealot thanks for your reply...if possible we can communicate pcie gen2 x4 via bar address to perform read/write via python in Linux?

@FPGAZealot Жыл бұрын

@@trendmakerzz7453 you can use mmap and np array to read direct memory in Linux with Python.

@trendmakerzz7453 Жыл бұрын

@@FPGAZealot can you please share me if you have any reference python file to read bar address memory space data in python Linux...

@trendmakerzz7453 Жыл бұрын

Hi why pcie xilnx memory controller am trying to read data from bar address but am getting response like 0xffffffff in both windows 10 and ubuntu...how to fix these issues yu have any idea pls suggest me...