Abhi 2 ghante bad exam h

Kal exam h

☝️

Few hours

15 mins bad hain exam 10.30 baje

pravin naga learning this in a university? I can how shitty your university is lmao

@@hanul4989 so what I am also learning this University's second year 3rd semester.

Good for you

I'm doing it in 2nd sem B.Sc

@@thehaseeb9136 same bro

47746cccv4555

Is she is from kenya

Yes!

No, it's correct. what you are describing is done when *negative edge trigger* is used. here we are using *positive edge trigger*

Bro try here 13:28

Well done....++

for positive edge trigger clock is taken from qa' . for negative edge trigger qa is taken as clock

🤣🤣👍👍👍

Both is same doesn't matter whether it is from q1 or q2

Yep she made a mistake

For up counter,If connected from q then clk should have bubble ie +- or q bar connected to clk ie -+ both valid I guess

@Aravind Badrinathan Thank You So much Sir !

If not use the toggle the second output will not come after the first output there is no change if not use the toggle flip flop

yes

The principle is for flip flop 1 u need external clock pulse , and for flip flop 2 it takes the output of flip flop 1 as clock pulse , This type of counter is known asynchronous counter !!

Can we give the out put of Q1 as clock ip to the next flip flop and why should we give the complement of Q1 as ip to the next flipflop can u say the difference between this two?

if you apply correct logic anything would work

Yes bro

This is positive triggered edge.

Least significant bit and most significant bit

@@shruthijeevanandam3379 suppose 4 bit counter are there ??howwe take msb and lsb

@@shruthijeevanandam3379 hi

@@sasireddy2544 left most flip flop output is always lsb and the right most flip flop output is msb

I don't think it is possible with them as they do not have a toggle condition.