Learn about the RISC-V instruction set architecture by building hardware. In this video, I use Logisim to build the Brancher that will eventually be incorporated into an RV32I CPU that can be synthesized on to an FPGA.
The brancher provides important control signals that enable the CPU to alter the program counter to jump to arbitrary locations in memory based on numeric comparisons.
There are a number of resources that I recommend you study as you go on this journey with me:
RISC-V Reference Card: www.cl.cam.ac.uk/teaching/161...
Design of the RISC-V Instruction Set Architecture: digitalassets.lib.berkeley.ed...
Great Ideas in Computer Architecture (week 2 and 4): inst.eecs.berkeley.edu/~cs61c...
RISC-V Specification: riscv.org/wp-content/uploads/...
Other helpful resources:
Online RISC-V assembler: riscvasm.lucasteske.dev
Logisim Evolution: github.com/logisim-evolution/...