Qualifiers...thanks. I'm edge of genx, so recall is fading ;-) I think this is related to optimization, but, full disclosure...I used chatgpt to help me figure out a solution. Re your C code comment...yeah. This is why I was confused in the first place. I did enjoy playing around with C3... chatgpt.com/share/2c82d6fe-913e-4bca-9819-e28dfaf57788

I appreciate that!

Glad you like it. Thanks.

Well, I put this out over the weekend...so pretty recent. I have two streams going...Risc-V Logisim SOC build and Risc-V bare metal sw. I am working on a bare-metal MicroPython with a REPL over serial and flash boot, at the moment. I stopped the Logism stream for a time but am planning to pick them back up. Which type are you hoping for?

Thanks!

Glad you enjoyed it!

Thanks for the kind words.

Thanks for the kind words.

Since the GNU linker is used by both, the syntax should port no problem. What the compilers emit may differ, however, plus the platform matters too, and so I suspect that's why a generalized linker script is so freakin' complicated. Running `riscv64-unknown-elf-ld --verbose` is educational. Re other languages, I am working on Python right now. Thinking about Go. I actually ported a version of Java to run bare metal on rPi years ago. I thought about revisiting that project for Risc-V. I've never used Rust or Zig. But sure, why not? Funny enough, there is no mov instruction for Risc-V. There is a mv psuedo instruction, `mv rd, rs`, which translates to `addi rd, rs, 0`, with the destination register being first. I find the green sheets helpful, for example: www.cs.sfu.ca/~ashriram/Courses/CS295/assets/notebooks/RISCV/RISCV_GREEN_CARD.pdf The FIFO is actually used, it's just never filled. THRE clears before the shift register finishes munching on its data. I wanted to show a technique that would prevent data from being dropped, not optimize throughput. But your point is valid. I was not clear in the video. Great questions. Thanks!

LLVM’s lld is a drop in replacement for GNU ld, so it should be identical. Rust and Zig are using LLVM so again, same scripts. (Zig wants to get rid of LLVM) There is also mold which is also a drop-in replacement. So you can use the same script with any of those three linkers.

silence instead?

My pleasure. I always learn something when I do these.

Agreed! I'm working on another rendition of this explainer, but for C instead. Should be out next few days.

Oh ignore me. I figured it out.

I am glad you did. I did that work some time ago and the answer was not readily apparent. I should have said as much. Care to share?

@@chuckbenedict7235 lol. Now you have me on the back foot. I recall looking again at the alu design and thinking about it again. I've since bought the book. I think (and I'm s bit hazy on this) it's because for x-y we negate y and then negate the output. Something about how the two negates work.. ? Maybe. 🤣🤣

I did model it at the time in logisim and proved that the approach of inverting and adding one doesn't work with the hack alu.

Logisim Evolution. You can download it here: github.com/logisim-evolution/logisim-evolution

I assumed that words are stored big endian in RAM. The spec says it can be done either way. It's easier to demo imho. Regarding use of mux for byte extraction...interesting. How would you propose? My hw implementation was based on me writing some pseudo code (which I did off camera), and shifting is what I envisioned.

Maybe 8 4-bit muxes with the 1st mux inputs on input b0,b8,b16,b24 outputting to b0, 2nd on b1,b9,b17,b25 outputting to b1 etc. The 2 bit selects are common to all 8 muxes. I think its the same or similar technique you used for the half word but not sure. The mux effectively performs the 0,8,16 or 24 bit byte shift depending on the select.

RISC-V is an open source instruction set architecture developed by UC Berkley. RISC means reduced instruction set computer...meaning that the CPU contains a small number of simple instructions. It is an ideal platform for learning more about CPUs. My Logisim series demonstrates how to go about building a functional CPU that can be synthesized on to an FPGA.

​@@chuckbenedict7235oh ty

Sorry to hear. You can get a new hot air rework station for under $80 from Ali Express. Get flux as well. Probably can get a used one for less on eBay. You could also try a local college...they have labs they might let you use, or fix it days.

Thank you, I will

I am building modules step by step, that will be combined into a design, which will implement a RISC-V system on a chip, in Logisim. The immediate generator acts upon RISC-V immediate instruction types, which contain hard-coded values within the instruction. Those immediate values are then needed by other modules (such as the ALU). Perhaps I did not add enough context at the beginning of the video. Have you have seen other videos in the series? I am about to deploy content on control logic, which pulls these modules together. Thanks for the question.

Thanks! Check out my RISC-V I32 series. I'm working on the next installment today.

Have a specific question that I can clear up?

Thanks for the kind words. My last series on the Hack CPU was a limited niche. I am not surprised at the limited uptake to date. RISC-V has broader appeal. So I expect the channel will grow. Or not. I do this because it helps reinforce my learning, with the hope that others will benefit. I do have bigger plans for this series...from building a compiler, to application of machine learning to Logisim. Cheers.

@chuckbenedict7235 I'll definitely watch your risc-v series as you make it. I started learning about computers about a year ago, and I was surprised by that lack of detailed how-to videos. I, too, have made quite a few logic related and cpu building videos in the hopes of making it easier to learn for other people who get into computer building.

Thanks, will do!

I try to put in as much of the learning and trials I had along the way. Kind words appreciated.

Sorry, I do not.

@@chuckbenedict7235 ok sir , thanks for responding 🙏🙏🙏

I didn't do it for clicks...I just had an interest. But I do appreciate the feedback and am glad you find it useful. Is there anything else you might find helpful if I were to start another series?

​ @chuckbenedict7235 That is such a difficult question haha. I personally would love to see a series on GPUs but that wouldn't really cater to a larger audience I think. You could try out hardware implementation of the hack architecture and maybe build a PCB surrounding it. The learning process itself is amazing. I too am working on the same thing and I plan to show it at our college exhibition in like a year. I have barely barely started with it (the parts aren't really very easy to find where I live) but I do hope to at least get far enough.

Thank you. Hope you find the content helpful.

That error usually is because of feedback but I cannot specifically answer without a circ to study.

Not legally as far as a know. I do see it available used on Amazon for $28. It is a good value for what is learned IMHO (I have nothing to do with the book btw).

Belated...you are welcome!

Thanks!

You're welcome

Thanks!

Awesome, thank you!

It has been educational for me putting it together. I am happy it has helped you. Thanks for the support.

Correct. Thx!

Thank you!

Thanks!

I am glad you are finding them useful. I have one more video to go for VGA to show the driver working under HackCPU control. Then yes...a keyboard driver will be next. I intend to start with PS2 since it is simple. I have sights set on a USB HID host, but it will take some time...how about HDMI?

@@chuckbenedict7235 That's awesome, I was only really expecting PS2 so hearing we might get some USB videos in the future is fantastic.

Now that VGA is working I'll be turning to PS2 input...stay tuned for a first drop in the next week or two. I hope that Pong will then work.

@@chuckbenedict7235 Awesome! I can't wait to see how you do it. I couldn't help myself and started learning about data and address bussing, but I really can't wait to see how it's done with the HackCPU

Oops...my bad and thanks for the tip.

Should be easier than building it with TTL chips. :-)

dude i built it already

I am glad you found value from the series. I continue to add to the collection.

Cross reference page 37 with page 67. I struggled with this too until I made the connection. There is an important one-liner in the last sentence of the Figure 4.3 caption: "Note the similarity between this instruction set and the ALU specification given in figure 2.6". I wrote, in my copy of the book, the bit descriptions over the c(x) columns on page 67. I have the earlier edition, by the way...

@@chuckbenedict7235 Thank you very much

My pleasure!

Welcome!

I intend to...I have been away for a time, but am working on more content right now. My goal is to assemble a complete working computer with a display and keyboard, with an assembler monitor application. What would you like to see?

@@chuckbenedict7235 I would like a tutorial on just like what you said you are working on, in Logisim of course. If you can't though, its fine! :D just continue this series if you can. No pressure man!

@@KapPetrov Yeah I'd like to see that too. Yah know, if this could be created in logism, this can be created in real life. That would be soo cool don't you think Kap Petrov?

@@oats7924 well yes! Im actually into breadboards now, im gonna buy one today. Obsessed with breadboards now! you should check it out too.

If you have not seen yet...I have VGA content posted and am working on the testing video today.

Most cards are reference designs, so I'd be surprised...snap in maybe? They have to attach somehow. I have not seen the model you reference.