Wall of text incoming! 1. Your yellow 16M module is essentially "double-sided", it consists of 8 8-bit chips which gives you a 64-bit module. It uses 2M 8-bit chips that have different rows and columns count, unlike 4M 4-bit chips with the same rows & columns count on the double-sided module. Late 486 and pretty much all P1 boards are able to use such chips. When you use such module as the first one, your motherboard will most probably treat all other modules in the bank like it has unequal rows & columns number too. This is why it works with 64-bit 16M module as primary and 32M as secondary: one row or column of the 32M module is ignored so you get 16M out of that one too. 2. Most motherboards ignore "presence detect" pins, even early 486 ones. 3. EDO modules work as FPM in almost every situation if you lift /OE pin from ground and connect it to /CAS (which is right next to it). If you look at timing diagrams, you will see that this way your EDO chip will match FPM timings quite closely. Also there's at least one 386 chipset that works with 30-pin EDO modules - Ali M1217. 4. Often you can determine a faulty memory line with a multimeter in diode mode. A bad line will have different voltage drop to ground/Vcc compared to working ones. 5. Another way to find a faulty pin would just to poke around with a digital scope, however not everybody has such equipment. 6. Be aware that 2/3-chip 4MB 30-pin modules will not work properly on certain 386 motherboards (with Macronix chipset, specifically), because those 4M 4-bit chips are refreshed differently compared to 4M 1-bit chips on 8/9 chips modules. If you have errors in 8-16M and 24-32M range after some time, this is a refresh issue and nothing can be done about that. 7. This problem (with unstable faulty data/address lines) is quite common with 3dfx Voodoo 1 cards, however it often happens on the GPU side, not on memory side. It almost never happens on cards which have resistors between GPU and memory. 8. I've had success with Memtest 4.10 on 386. 9. Good luck! =)

You could take a single chip off the working module and swap U6 out with it. then U14, then U5, then U13 and see if the 2nd pass errors persist between swaps.

I see Bits und Bolts on my timeline y stop looking for content and relax, thanks!

This is great, exactly the kind of odd in detail videos about oldish computer hardware that i love.

I'm in DIZZY condition after watching this video, congratulations.

Nice rabbit hole! I understand the curiosity though, I am the same sometimes :) I'm curious to see the outcome!

A lot of work has been done! Awesome!

Taking this hobby to the next level!

Yeah, theoretically EDO memory _should_ work in FPM mode, but I vaguely remember there are differences between the timing diagrams of the two, so it's possible the chips could latch the address bus before it's settled, or output the data too early and cause a bus conflict (it's been a couple of years since I researched it, so I don't remember which one is more likely). That being said, the first batch of 30-pin SIMMs that I assembled used EDO memory, and they tested fine in my memory tester, but I never went on to test them in a PC since the only machine I had at the time that used 30-pin SIMMs was a Mac SE/30, which also needed the parity chips, but I didn't have any. They were recognised as EDO in my tester, so obviously it was using the correct timings for EDO rather than FPM. I have since acquired a couple of motherboards that take 30-pin SIMMs, but I've also gotten deep into electronics projects, so all my boxes of electronic components are stacked in front of my shelves and workbench that I use to store my vintage computer parts and work on those PCs. My apartment is so tiny, I've literally only got enough room to pull out one box of parts at a time, so I can't clear enough room in front of my workbench to work on any vintage PC projects.

Yes they should work fine in fast page mode. EDO DRAM and FP DRAM are functionally identical the EDO simply has the additional EDO mode enabled by a signal Pin.

Cant wait for a follow up video. Great 👍

Enjoy your T56. That clip is for a dip8 chip. The t56 is a bit of a rabbit hole regarding buying various adapters to attach different form factors. I've spent twice the cost of the device on adapters.

Interesting video, like!

Hi very nice Video ! Why don't you use a different test pattern in memtest+ ? don't use random pattern, use a sorted pattern were you can see at what addresses the error start to occur.

Admirable work

if you are swapping chips, it might be easier to swap chips on the same side of the same chip, you should then get a different bit pattern for the error.

I heard of adapters meant to use 30 pin RAM sticks in 72 pin memory slots; can be made the other way around, I guess. The EDO chips I remember that fall back in FPM mode when used in mixed configurations, at least in older 486 boards (on mine I had EDO/FPM 72 pin + 30 pin memories)

Hey, really nice video, keep it up man! Regarding your testing: why do you resort to the "8 slots" paradigm when mapping errors? Doing it like that means that you loose the "down to exact bit" granularity. You've got 64bits data bus with 32bits assigned to each of modules in a pair. Splitting them into mere 8 groups means that you won't be able to distinguish situations when 8 sequential bits from the memory controller POV are actually connected to either the same or to different SIMM chips. You really need to get down to actual bits instead of "8 slots" to analyze it properly. When you see an error appearing in "slot X" with error bits number being, say, 4 - it's actually a totally different error location compared to the same slot X but, say, error bit number 2. There's a complication in here (of course there is at least one, who would have thought!) - actual mapping of data bits to the data lines may be dependent on the address of the memory accessed. It comes as a consequence of a more "smart" chipsets having memory controllers doing things like interleave which may - in some cases - result in better stability and less power consumption. Results shown in the video suggest that the MB with "more logical pattern" has a memory controller and board layout running in a simpler "more dumb" mode - which is a good thing from the debugging POV you do to nail it out. If you've got an opportunity to use third MB to do the same tests - it might allow you to nail it down to the single faulty chip.

Because for this CPU you need at least 2 SIMMs to fill its Data BUS, on a 386DX or 486 they will work individually, Pentiums need a pair which will act as a single module.

Awesome work! I would recommend you to test with an oscilloscope if the response of each chip is correct between them, but i dnt have (yet) the expertise to know if it will work or not. Following you every step of the journey from argentina!

Super Video! Ich kann ungefähr nachvollziehen wie viel Zeit und Arbeit in deine Untersuchungen und die Erstellung des Videos gegangen sind. Repariere momentan ein Shuttle 386er Board wegen der ausgelaufenen Batterie und habe nach mittlerweile 10h Arbeit das Ziel in Sicht. Es fehlen aber noch ca 8 Bodgewires um die zerstörten Leiterbahnen zu ersetzen.

Ooh, I think I have that same Abit board. I also have a 512k SRAM module :)

you are lucky the error bits are consistent. Modern(ish) systems use "scrambling" where the data value written to memory is XORed or swizzled on write and read with a known value (derived from physical address in systems I am aware of) so that repeated writes of constant values over a continuous addressable block of memory doesn't cause a consistent RF transmission pattern. the ordering of the data lines does not have to match the JEDEC data pin numbering, as you discovered when moving the module between different motherboards. I bet there is also some flexibility with the address mapping as well, (to simplify trace routing,) so some motherboards may map the physical chips differently into the memory map, kind of an intra-module interleaving. I don't know if the micro-architecture specs for these old northbridges are still available, I wonder if standalone memory module testers exist which would make the process of identifying individually failed chips less time- and effort-consuming?

I have a TMC board which states that slot 3 is infact bank 0 and not 2. Quite confusing!

Would stacking a working memory chip on top of another memory chip work? Not to double the capacity but to see if the error goes away with the chip on top of a faulty chip.

Do you have a thermal camera? I would be interested to see the output after the second failed loop runs for a while.

I'm flummoxed by the end segment. If the motherboard allowed only one SIMM to be populated, then it should have been running at half the speed of the paired combos. Maybe because you plugged in only one, it flipped a bios setting forcing it to do double reads which persisted to when you put it back in paired mode ??

1. I don't expect 5V problems on these lines as that's the memory design, and the NB would "translate" that to 3.3V of Pentium. Those memories were made for 5V 486es, which means they output 5V. Of course, shorting to VSS or VCC would be worse than shorting 2 lines, as it would allow more current. 2. I think you could isolate the sides using RAS/CAS. I expect one side to be at RAS0/CAS0 on 72-pin and the other side at RAS1/CAS1. If you short (small resistor strongly recommended) these to VCC, you would disable one side. 3. try to find a pattern in the addresses reported by memtest. At 3:19, I see addresses ending in 20, 40, 60, a0, c0. They seem to be 32-byte multiples, so 16-bytes relevant to 1 module. Since you have 8 bytes/transactions/module, looks like a stuck A0 on 1 chip (considering the last addresses are 20, 40, 60, a0, c0, all "even", I would say a stuck at 1). Seeing it at 24MB out of 64MB (so 12MB out of 32), the chips might be actually 4 chips internally separated by 2 high address lines. 4. Something maybe against 3., as you saw between the 2 motherboards, the data lines might be scrambled (remapped), also hinting the same for the address lines. My 3. conclusion was that A0 separates consecutive addresses, but the controller could interleave RAS0+CAS0 and RAS1+CAS1. I.e.: consecutive addresses of A0+RAS0, A0+RAS1, (A0+1)+RAS0, (A0+1)+RAS1 instead of A0+RAS0, (A0+1)+RAS0,....,A0+RAS1, (A0+1)+RAS1. So my 3. conclusion could also be a RAS/CAS stuck at 1. 5. Longshot: use an oscilloscope to see the data lines on chips. You might see a pattern of good data vs. bad data. The longshot part is that this includes the writing to the chips which could hide a consistent stuck output. Edit: just realized the memory schematic. Regarding point 2, I see all 4 RAS/CAS lines are used. Since the 24/64MB location (12/32 of 1 module), I would suspect chips that use RAS1. But, MB scrambling would alter this. Either way, pulling-up 1 RAS+CAS set would present new info.

If you desoldered memory chips already, try to test them in your programmer. Maybe you've get lucky.

Cursed memories

Was it worth it...

just use the piggy back method

Find a gpu with removable ram chips and you should quickly find what chip is bad

Why that madness if you have failing address? Figure out where computer land that address and you have the answer

Never touch chip pins or the modules connectors if you don't use an ESD strap.

I registered Win Me by sending a fax to my fax inbox, and sent it back to my computer. It needed 4 retries to receive a full A4 page. When succeeded, my Windows became legal. I used awafax, outlook 97 and Exchange. The computer became as stable as a Win7. This trick can be done with Dos, Win 3.x, 9x, etc. when done, the legal win will fix bad computer parts.