16. episode in a series where we dive into FPGA Development! We are following an FPGA Academy Course, which can be found here fpgacademy.org/
In this episode, we will be going through a tutorial on Digital Logic Simulation and Debugging. We will show you how to set up timing constraints and obtain timing information for a logic circuit using the Quartus Prime Timing Analyzer. To demonstrate this, we will go through a simple example.
-- Watch the following parts live on Twitch www.twitch.tv/bracketscoding